1
Steven L Gregor: Store queue for a tightly coupled multiple processor configuration with two-level cache buffer storage. International Business Machines, David S Romney, John H Bouchard, June 11, 1991: US05023776 (155 worldwide citation)

A multiprocessor system includes a system of store queues and write buffers in a hierarchical first level and second level memory system including a first level store queue for storing instructions and/or data from a processor of the multiprocessor system prior to storage in a first level of cache, ...


2
Patrick W Gallagher, Steven L Gregor, Stephen M Reeve: Shared two level cache including apparatus for maintaining storage consistency. International Business Machines Corporation, Arthur J Samodovitz, Pryor A Garnett, Hugh Jaeger, January 4, 1994: US05276848 (118 worldwide citation)

A multilevel cache buffer for a multiprocessor system in which each processor has a level one cache storage unit which interfaces with a level two cache unit and main storage unit shared by all processors. The multiprocessors share the level two cache according to a priority algorithm. When data in ...


3
Steven L Gregor, Robert A Iannucci: System for synchronizing execution by a processing element of threads within a process using a state indicator. International Business Machines Corporation, Heslin & Rothenberg P C, September 3, 1996: US05553305 (52 worldwide citation)

A method and system for synchronizing execution by a processing element of threads within a process. Before execution of a thread commences, a determination is made as to whether all of the required resources for execution of the thread are available in a cache local to the processing element. If th ...


4
R Dean Adams, Thomas J Eckenrode, Steven L Gregor, Kamran Zarrineh: Programable multi-port memory BIST with compact microcode. Cadence Design Systems, Orrick Herrington & Sutcliffe, January 23, 2007: US07168005 (47 worldwide citation)

A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit ...


5
Steven L Gregor: Storage protection keys in two level cache system. International Business Machines Corporation, Arthur J Samodovitz, September 12, 1995: US05450563 (37 worldwide citation)

The cache system comprises a level one (L1) data cache, a level one (L1) key cache for storing a plurality of access keys for respective pages or blocks of data referenced by the central processor. A level three (L3) storage stores the data requested by the central processor and an access key array ...


6
R Dean Adams, Thomas J Eckenrode, Steven L Gregor, Kamran Zarrineh: Method and apparatus for testing multi-port memories. Cadence Design Systems, Orrick Herrington & Sutcliffe, April 29, 2003: US06557127 (37 worldwide citation)

A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not ...


7
Steven L Gregor, Victor S Lee: Direct hardware error identification method and apparatus for error recovery in pipelined processing areas of a computer system. International Business Machines, May 8, 1990: US04924466 (32 worldwide citation)

A computer system having trace arrays and registers that provide error tracing that permits retry of operations in a pipelined, multiprocessing environment after the operations have been allowed to quiesce. The trace arrays in each retry domain include one master trace array. The master arrays store ...


8
R Dean Adams, Thomas J Eckenrode, Steven L Gregor, Kamran Zarrineh: System initialization of microcode-based memory built-in self-test. International Business Machines Corporation, Whitham Curtis & Christofferson P C, Joseph P Abate, March 29, 2005: US06874111 (17 worldwide citation)

The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in se ...


9
Steven L Gregor: System for execution of storage-immediate and storage-storage instructions within cache buffer storage. International Business Machines, Lynn L Augspurger, July 6, 1993: US05226169 (16 worldwide citation)

A cache storage system having hardware for in-cache execution of storage-storage and storage-immediate instructions thereby obviating the need for data to be moved from the cache to a separate execution unit and back to cache.


10
R Dean Adams, Thomas J Eckenrode, Steven L Gregor, Kamran Zarrineh: Programmable memory built-in self-test combining microcode and finite state machine self-test. International Business Machines Corporation, Joseph P Abate, Whitham Curtis Christofferson P C, November 18, 2003: US06651201 (16 worldwide citation)

A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruc ...