1
Katherina Babich
Scott D Allen, Katherina E Babich, Steven J Holmes, Arpan P Mahorowala, Dirk Pfeiffer, Richard Stephan Wise: Techniques for patterning features in semiconductor devices. International Business Machines Corporation, Ryan Mason & Lewis, Daniel P Morris, April 18, 2006: US07030008 (6 worldwide citation)

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithograph ...


2
Katherina Babich
Scott D Allen, Katherina E Babich, Steven J Holmes, Arpan P Mahorowala, Dirk Pfeiffer, Richard Stephan Wise: Techniques for patterning features in semiconductor devices. International Business Machines Corporation, Daniel P Morris Esq, Ryan Mason & Lewis, June 9, 2009: US07545041 (2 worldwide citation)

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithograph ...


3
Katherina Babich
Scott D Allen, Katherina E Babich, Steven J Holmes, Arpan P Mahorowala, Dirk Pfeiffer, Richard Stephan Wise: Techniques for Patterning Features in Semiconductor Devices. International Business Machines Corporation, Ryan Mason & Lewis, August 7, 2008: US20080187731-A1

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithograph ...


4
Katherina Babich
Scott D Allen, Katherina E Babich, Steven J Holmes, Arpan P Mahorowala, Dirk Pfeiffer, Richard Stephan Wise: Techniques for patterning features in semiconductor devices. International Business Machines Corporation, Ryan Mason & Lewis, June 8, 2006: US20060118785-A1

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithograph ...


5
Katherina Babich
Scott D Allen, Katherina E Babich, Steven J Holmes, Arpan P Mahorowala, Dirk Pfeiffer, Richard Stephan Wise: Techniques for patterning features in semiconductor devices. International Business Machines Corporation, Ryan Mason & Lewis, March 17, 2005: US20050056823-A1

Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithograph ...


6
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III: Accessible chip stack and process of manufacturing thereof. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Joseph Petrokaitis Esq, May 5, 2009: US07528494 (161 worldwide citation)

A process of manufacturing a three-dimensional integrated circuit chip or wafer assembly and, more particularly, a processing of chips while arranged on a wafer prior to orienting the chips into stacks. Also disclosed is the manufacture of the three-dimensional integrated circuit wherein the chip de ...


7
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Paul A Rabidoux: Method for forming pillar memory cells and device formed thereby. International Business Machines Corporation, Eugene I Shkurko, Schmeiser Olsen & Watts, August 1, 2000: US06096598 (136 worldwide citation)

The preferred embodiments of the present invention overcome the limitations of the prior art by providing a method for forming the source/drain diffusions in a vertical transistor structure that results in improved channel length uniformity. In one embodiment, the present invention is used to form s ...


8
Toshiharu Furukawa, Mark Charles Hakey, Steven J Holmes, David V Horak, Charles W Koburger III, Chung Hon Lam: Methods for forming uniform lithographic features. International Business Machines Corporation, Keusey Tutunjian & Bitetto P C, April 1, 2008: US07351648 (118 worldwide citation)

Methods for fabricating a semiconductor device include forming a first layer on an underlying layer, forming a hardmask on the first layer, and patterning holes through the hardmask and first layer. An overhang is formed extending over sides of the holes. A conformal layer is deposited over the over ...


9
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Howard L Kalter, Jack A Mandelman, Paul A Rabidoux, Jeffrey J Welser: Structure for folded architecture pillar memory cell. International Business Machines Corporation, Mark F Chadurjian, Scully Scott Murphy & Presser, August 27, 2002: US06440801 (106 worldwide citation)

A densely packed array of vertical semiconductor devices having pillars and methods of making thereof are disclosed. The array has rows of wordlines and columns of bitlines. The array has vertical pillars, each having two wordlines, one active and the other passing for each, cell. Two wordlines are ...


10
Toshiharu Furukawa, Mark C Hakey, Steven J Holmes, David V Horak, Charles W Koburger III: Field effect transistor. International Business Machines Corporation, Schmeiser Olsen & Watts, Richard M Kotulak, August 23, 2011: US08004024 (83 worldwide citation)

A transistor. The transistor including: a well region in a substrate; a gate dielectric layer on a top surface of the well region; a polysilicon gate electrode on a top surface of the gate dielectric layer; spacers formed on opposite sidewalls of the polysilicon gate electrode; source/drain regions ...



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