1
Steven Avanzino, Subhash Gupta, Rich Klein, Scott D Luning, Ming Ren Lin: Self aligned via dual damascene. Advanced Micro Devices, Foley & Lardner, March 25, 1997: US05614765 (85 worldwide citation)

An interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask pattern of conductive li ...


2
Steven Avanzino, Subhash Gupta, Rich Klein, Scott D Luning, Ming Ren Lin: Dual damascene with a sacrificial via fill. Advanced Micro Devices, Foley & Lardner, January 6, 1998: US05705430 (71 worldwide citation)

A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a sacrificial via fill. A first layer of insulating material is formed with via openings. The ...


3
Nicholas H Tripsas, Colin S Bill, Michael A VanBuskirk, Matthew Buynoski, Tzu Ning Fang, Wei Daisy Cai, Suzette Pangrle, Steven Avanzino: Diode array architecture for addressing nanoscale resistive memory arrays. April 25, 2006: US07035141 (63 worldwide citation)

The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the fi ...


4
Steven Avanzino, Subhash Gupta, Rich Klein, Scott D Luning, Ming Ren Lin: Self aligned via dual damascene. Advanced Micro Devices, Foley & Lardner, August 18, 1998: US05795823 (51 worldwide citation)

A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using dual damascene with only one mask pattern for the formation of both the conductive lines and vias. The mask ...


5
Steven Avanzino, Subhash Gupta, Rich Klein, Scott D Luning, Ming Ren Lin: Dual damascene with a protective mask for via etching. Advanced Micro Devices, Foley & Lardner, November 11, 1997: US05686354 (39 worldwide citation)

A dual damascene method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a thin protective via mask to form the via openings. A conductive line mask pattern is used t ...


6
Steven Avanzino, Darrell Erb, Robin Cheung: Uniform nonconformal deposition for forming low dielectric constant insulation between certain conductive lines. Advanced Micro Devices, Foley & Lardner, November 17, 1998: US05837618 (32 worldwide citation)

A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4 ...


7
Steven Avanzino, Darrell M Erb, Robin Cheung, Rich Klein: Composite insulation with a dielectric constant of less than 3 in a narrow space separating conductive lines. Advanced Micro Devices, Foley & Lardner, November 25, 1997: US05691573 (29 worldwide citation)

A method of forming low dielectric insulation between those pairs of conductive lines, of a level of interconnection for integrated circuits, having a gap of about 0.5 microns or less by depositing a nonconformal source with a poor step function for the insulating material, such as silane (SiH.sub.4 ...


8
Richard K Klein, Darrell Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming Ren Lin: Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device. Advanced Micro Devices, Foley & Lardner, June 23, 1998: US05770519 (27 worldwide citation)

A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A b ...


9
Kai Yang, Steven Avanzino, Christy Mei Chu Woo: Slurry for chemical mechanical polishing of copper. Advanced Micro Devices, November 7, 2000: US06143656 (26 worldwide citation)

Copper metalization is planarized by CMP employing a slurry which avoids scratching the copper surface and is highly selective to the underlying barrier layer. Embodiments include CMP a copper filled damascene opening using a slurry comprising about 0.2 to about 0.7 wt. % Al.sub.2 O.sub.3 and about ...


10
Steven Avanzino, Subhash Gupta, Rich Klein, Scott D Luning, Ming Ren Lin: Subtractive dual damascene. Advanced Micro Devices, Foley & Lardner, November 25, 1997: US05691238 (22 worldwide citation)

A method of fabricating an interconnection level of conductive lines and connecting vias separated by insulation for integrated circuits and substrate carriers for semiconductor devices using a reverse damascene in the formation of the conductive lines and vias. A conductive line pattern is first us ...