1
John P Moussouris, Lester M Crudele, Steven A Przybylski: Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories. MIPS Computer Systems, Kenyon & Kenyon, August 28, 1990: US04953073 (84 worldwide citation)

A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating ...


2
Larry B Weber, Craig C Hansen, Thomas J Riordan, Steven A Przybylski: Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders. Mips Computer Systems, Kenyon & Kenyon, September 25, 1990: US04959779 (81 worldwide citation)

A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme ...


3
John P Moussouris, Lester M Crudele, Steven A Przybylski: System having an address generating unit and a log comparator packaged as an integrated circuit seperate from cache log memory and cache data memory. MIPS Computer Systems, Kenyon & Kenyon, May 12, 1992: US05113506 (47 worldwide citation)

A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, ...


4
Steven A Przybylski: Ring-of-clusters network topologies. MOSAID Technologies Incorporated, Don Mollick, Daniel Hammond, Shuji Sumi, November 26, 2013: US08594110

In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that ...


5
Hong Beom PYEON, HakJune OH, Jin Ki KIM, Steven A PRZYBYLSKI: Id generation apparatus and method for serially interconnected devices. Mosaid Technologies Incorporated, Dennis R Haszko, Patent Law Office of DRHaszko, June 26, 2008: US20080155219-A1

A plurality of memory devices (e.g., DRAMs, SRAMs, NAND Flash, NOR Flash) is serially interconnected. Each of the interconnected devices receives a device identifier (ID) and latches it as its ID. Each device includes a circuit for calculating another ID or an incremented ID to generate it. The gene ...


6
Steven A Przybylski: Ring-of-clusters network topologies. MOSAID Technologies, Gifford Krass Sprinkle Anderson & Citkowski PC, July 16, 2009: US20090180483-A1

In a ring-of-clusters network topology, groups of slave devices are accessed in parallel, such that the latency around the ring is proportional to the number of clusters and not proportional to the number of integrated circuits. The devices of a cluster share input and output ring segments such that ...