1
Darrell D Rinerson, Steve K Hsia, Christophe J Chevallier, Chan Sui Pang: Memory array architecture for flash memory. Catalyst Semiconductor Corporation, Skjerven Morrill MacPherson Franklin & Friel, February 9, 1993: US05185718 (54 worldwide citation)

Disclosed is a EEPROM flash memory array utilizing single transistor cells to provide read/write nonvolatile storage. The array includes a plurality of sectors, each oriented along the word line direction, and the sectors may include one or more word lines. An erase select transistor is provided for ...


2
Christophe J Chevallier, Asim A Bajwa, Darrell D Rinerson, Steve K Hsia: Memory circuit with pumped voltage for erase and program operations. Catalyst Semiconductor, Skjerven Morrill MacPherson Franklin & Friel, May 17, 1994: US05313429 (52 worldwide citation)

A memory device is disclosed that employs hot electron injection for programming operations and Fowler-Nordheim tunneling for erase operations. The memory device requires only a single 5 volt power supply and does not require an external high voltage supply for program or erase operations. The memor ...


3
Steve K Hsia, Chan Sui Pang, Christopher J Chevallier: High density EEPROM cell and process for making the cell. Catalyst Semiconductor, Skjerven Morrill MacPherson Franklin & Friel, July 16, 1991: US05033023 (36 worldwide citation)

Disclosed is a stacked gate electrically erasable programmable read only memory EEPROM cell which utilizes a floating region and a common pass transistor to provide a cell which is programmable at a relatively low drain voltage and which, in addition, by utilizing a pass transistor, overcomes the pr ...


4
Steve K Hsia, Pritpal S Mahal, Wei Ren Shih: Process for making a high density split gate nonvolatile memory cell. Catalyst Semiconductor, Skjerven Morrill MacPherson Franklin & Friel, August 29, 1989: US04861730 (35 worldwide citation)

A process is disclosed for producing a high density split gate nonvolatile memory cell which includes a floating gate and a control gate that is formed above the floating gate. The drain region is self-aligned to the floating gate and the source region is self-aligned to the control gate. Fully self ...


5
Steve K Hsia, Kyung Joon Han, Dung Tran: Method and apparatus for multiple byte or page mode programming of a flash memory array. NexFlash Technologies, Altera Law Group, June 8, 2004: US06747899 (28 worldwide citation)

A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate poten ...


6
Kyung Joon Han, Dung Tran, Steven W Longcor, Steve K Hsia: Method and apparatus for multiple byte or page mode programming of a flash memory array. NexFlash Technologies, Altera Law Group, May 4, 2004: US06731544 (22 worldwide citation)

A memory array contains memory cells designed to be erased using Fowler-Nordheim (“FN”) tunneling through the channel area, and programmed using either channel hot electron injection (“CHE”) or channel-initiated secondary electron injection (“CISEI”). To reduce disturbance of the floating gate poten ...


7
Kyung Joon Han, Steve K Hsia, Joo Weon Park, Gyu Wan Kwon, Jong Seuk Lee: Virtual ground single transistor memory cell, memory array incorporating same, and method of operation thereof. NexFlash Technologies, Altera Law Group, March 29, 2005: US06873004 (20 worldwide citation)

An asymmetrical virtual ground single transistor floating gate memory cell has a floating gate that overlies a channel region in a p-well, the channel region lying between a heavily doped n+ drain region and a lightly doped n− source region. A heavily doped p+ region known as a “halo” is disposed in ...


8
Steve K Hsia, Chan Sui Pang: Nonvolatile memory cell for eeprom including a floating gate to drain tunnel area positioned away from the channel region to prevent trapping of electrons in the gate oxide during cell erase. Catalyst Semiconductor, Skjerven Morrill MacPherson Franklin & Friel, January 16, 1990: US04894802 (20 worldwide citation)

Disclosed is a nonvolatile memory cell which utilizes a tunnel window to discharge the floating gate at a location spacially displaced from the program path for the cell. Also disclosed is a process for making such a memory cell.


9
Makoto Nagashima, Darrell Rinerson, Steve K Hsia, Larry Matheny: Low temperature deposition of complex metal oxides (CMO) memory materials for non-volatile memory integrated circuits. June 20, 2006: US07063984 (7 worldwide citation)

A memory fabrication apparatus includes a pair of targets arranged so as to be spaced apart from one another within a closed vacuum vessel, each target of said pair of targets having a sputtering surface facing the sputtering surface of the other target of said pair of targets; and substrate holder ...


10
Kyung Joon Han, Joo Weon Park, Gyu Wan Kwon, Dung Tran, Steve K Hsia, Jong Seuk Lee, Dae Hyun Kim: Threshold voltage convergence. NexFlash Technologies, Altera Law Group, April 27, 2004: US06728140 (1 worldwide citation)

A convergence signal includes a series of voltage pulses used to perform a convergence procedure in one or more flash EEPROM memory cells (transistors). In one instance subsequent voltage pulses in the convergence signal each have a higher voltage than the preceding pulse. In another instance, subse ...