1
Stephen S Pawlowski, Peter D MacWilliams, D Michael Bell: Queue ordering for memory and I/O transactions in a multiple concurrent transaction computer system. Intel Corporation, Kenyon & Kenyon, May 18, 1999: US05905876 (93 worldwide citation)

A transaction ordering mechanism for processor-based computing systems ensures proper ordering of transactions between the processor, I/O and memory subsystems, ensures cache coherence within the computing system, and facilitates concurrence of the transactions so as to enable high-bandwidth, deadlo ...


2
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Quad pumped bus architecture and protocol. Intel Corporation, Antonelli Terry Stout & Kraus, July 29, 2003: US06601121 (63 worldwide citation)

A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of th ...


3
Stephen S Pawlowski, Mohan Kumar, David E Ackelson: Dynamic discovery of wireless peripherals. Intel Corporation, Kenyon & Kenyon, February 27, 2001: US06195712 (56 worldwide citation)

A “Plug and Play” type dynamic detection and binding capability for wireless peripheral devices is disclosed. The dynamic detection and binding of wireless peripherals is achieved without manual intervention, and without modifications to the host computing device's built-in operating system (BI ...


4
Nitin V Sarangdhar, Konrad K Lai, Gurbir Singh, Peter D MacWilliams, Stephen S Pawlowski, Michael W Rhodehamel: Method and apparatus for performing deferred transactions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 25, 1997: US05615343 (39 worldwide citation)

A method and apparatus of performing bus transactions on the bus of the computer system. The present invention includes a method and apparatus for permitting out-of-order replies in a pipelined bus system. The out-of-order responses include the sending of tokens between both the requesting agents an ...


5
Stephen S Pawlowski, Andrew F Glew, George R Hayek, Harshvardhan P Sharangpani, Richard C Calderwood: Method and apparatus for hazard detection and distraction avoidance for a vehicle. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 2, 1999: US05978737 (34 worldwide citation)

A system for detecting hazardous conditions during operation of a vehicle. In one embodiment, the system includes a plurality of sensors that monitor a plurality of conditions and transmit condition signals each representing a measure of a condition. A plurality of rate determination circuits is cou ...


6
Sham Datta, Mani Ayyar, Douglas Moran, Stephen S Pawlowski: Multi-processor system for selecting a processor which has successfully written it's ID into write-once register after system reset as the boot-strap processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 15, 2003: US06594756 (32 worldwide citation)

A bootstrap processor selection mechanism for a computer system employs system logic having a memory-mapped sticky, e.g. write-once, register, multiple processors, and a firmware routine through which the processors may store values to and load values from the sticky register. When a reset event is ...


7
Nitin V Sarangdhar, Gurbir Singh, Konrad Lai, Stephen S Pawlowski, Peter D MacWilliams, Michael W Rhodehamel: Highly pipelined bus architecture. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 18, 1998: US05796977 (25 worldwide citation)

A computer system incorporating a pipelined bus that maintains data coherency, supports long latency transactions and provides processor order is described. The computer system includes bus agents having in-order-queues that track multiple outstanding transactions across a system bus and that perfor ...


8
William S Wu, Stephen S Pawlowski, Peter D MacWilliams: Method and apparatus for performing TLB shutdown operations in a multiprocessor system without invoking interrup handler routines. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 18, 1999: US05906001 (25 worldwide citation)

Prior art methods of maintaining coherency among multiple TLBs in a multiprocessor system were time-consuming. One microprocessor halted all other microprocessors in the system, and sent an interrupt to each of the halted microprocessors. Rather than invoking an interrupt handler, the TLB shootdown ...


9
Stephen S Pawlowski, Daniel G Lau: System and apparatus including lowest priority logic to select a processor to receive an interrupt message. Intel Corporation, Alan K Aldous, July 9, 2002: US06418496 (25 worldwide citation)

One embodiment of the invention includes an apparatus, such as a bridge, for use in connection a with computer system. The apparatus includes remote priority capture logic to hold task priority data indicative of a task priority of each processor in the computer system that is available for lowest p ...


10
Stephen S Pawlowski: Method and apparatus for tracking transactions in a pipelined bus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 9, 1997: US05696910 (24 worldwide citation)

A method and apparatus for tracking transactions in a pipelined bus includes a bus state tracking queue and control logic. The bus state tracking queue maintains a record of bus transaction information for each of a plurality of transactions pending on the bus. The control logic, coupled to the bus ...