1
Stephen M Trimberger, Richard A Carberry, Robert Anders Johnson, Jennifer Wong: Time multiplexed programmable logic device. Xilinx, Jeanette S Harms, Norman R Klivans, July 8, 1997: US05646545 (343 worldwide citation)

A programmable logic device (PLD) comprises a plurality of configurable logic blocks (CLBs), an interconnect structure for interconnecting the CLBs, and a plurality of programmable logic elements for configuring the CLBs and the interconnect structure. Each CLB includes a combinational element and a ...


2
Stephen M Trimberger, Richard A Carberry, Robert Anders Johnson, Jennifer Wong: Method of time multiplexing a programmable logic device. Xilinx, Jeanette S Harms, November 12, 2002: US06480954 (255 worldwide citation)

A programmable logic device (PLD) comprises at least one configurable element, and a plurality of programmable logic elements for configuring the configurable element(s). Alternatively, a PLD comprises an interconnect structure and a plurality of programmable logic elements for configuring the inter ...


3
Stephen M Trimberger: PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays. Xilinx, Adam H Tachner, Jeanette S Harms, July 4, 2000: US06084429 (253 worldwide citation)

A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks ...


4
F Erich Goetting, Stephen M Trimberger: Logic cell for field programmable gate array having optional internal feedback and optional cascade. Xilinx, Edel M Young, November 15, 1994: US05365125 (247 worldwide citation)

The logic cell of the current invention is useful in a field programmable logic device, particularly a device in which an interconnect structure is interconnected by antifuses, and logic cells are programmed using pass transistors. All input leads of the logic cell can be selectively inverted. The o ...


5
Stephen M Trimberger: Method for making large-scale ASIC using pre-engineered long distance routing structure. Xilinx, Patrick T Bever, H C Chan, Edel M Young, July 29, 2003: US06601227 (247 worldwide citation)

Optimal routing line segments and associated buffers are pre-engineered for each family of ASIC chips by simulating wires segments of various lengths using distributed resistance and capacitance wire models, and by estimating crosstalk from neighboring line segments. During ASIC design, space is res ...


6
Danesh Tavana, Wilson K Yee, Stephen M Trimberger: Integrated circuit with field programmable and application specific logic areas. Xilinx, Edel M Young, Adam H Tachner, Lois D Cartier, October 20, 1998: US05825202 (235 worldwide citation)

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By int ...


7
Stephen M Trimberger: Optimizing and operating a time multiplexed programmable logic device. Xilinx, Jeanette S Harms, Norman R Klivans, June 2, 1998: US05761483 (228 worldwide citation)

A method of optimizing a time multiplexed programmable logic device (PLD) includes entering a circuit design for the PLD, mapping the design to the physical resources of the PLD (wherein the physical resources include configurable logic elements), determining an appropriate micro cycle for each conf ...


8
Stephen M Trimberger: Computer-implemented method of optimizing a time multiplexed programmable logic device. Xilinx, Jeanette S Harms, Norman R Skjerven Morrill MacPherson Franklin & Friel Klivans, October 20, 1998: US05825662 (208 worldwide citation)

A computer-implemented method of optimizing a time multiplexed programmable logic device includes identifying a micro cycle, identifying all look-up tables (LUTs) from a list of LUTs of the PLD that may be scheduled in the micro cycle, ordering the LUTs in priority order, selecting the M LUTs with t ...


9
Stephen M Trimberger: Field programmable gate array having programming instructions in the configuration bitstream. Xilinx, Edel M Young, LeRoy D Maunu Esq, April 6, 1999: US05892961 (202 worldwide citation)

A programmable gate array (FPGA) comprises a CPU coupled to a configuration memory array. Bitstream data used for configuring the configuration memory array is encoded to combine programming instructions and configuration data. The CPU receives and decodes the encoded bitstream data, and executes th ...


10
Stephen M Trimberger, Richard A Carberry, Robert A Johnson, Jennifer Wong: Method of time multiplexing a programmable logic device. Xilinx, Jeanette S Harms, Norman R Klivans, May 13, 1997: US05629637 (188 worldwide citation)

A method of time multiplexing a programmable logic device (PLD) includes inputting a design for the PLD and dividing an evaluation of the logic of the design into a plurality of micro cycles. The method further includes identifying the logic not within a critical path of the design and rescheduling ...