1
Eric M Schwarz, Stamatis Vassiliadis: Dynamic multiple instruction stream multiple data multiple pipeline apparatus for floating-point single instruction stream single data architectures. International Business Machines Corporation, David S Romney, John H Bouchard, April 10, 1990: US04916652 (177 worldwide citation)

A dynamic multiple instruction stream, multiple data, multiple pipeline (MIMD) apparatus simultaneously executes more than one instruction associated with a multiple number of instruction streams utilizing multiple data associated with the multiple number of instruction streams in a multiple number ...


2
Stamatis Vassiliadis, Eric M Schwarz: Generalized 7/3 counters. International Business Machines Corporation, Baker Maxham Jester & Meador, February 16, 1993: US05187679 (134 worldwide citation)

A generalized 7/3 counter is proposed that may have all, some, or none of the input elements negative. The generalized counter can be used in array multipliers and in general for the reduction of matrices which have rows that must be added and need the advantage of a carry-free addition for speed pu ...


3
Richard J Eickemeyer, Stamatis Vassiliadis, Bartholomew Blaner: In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution. International Business Machines Corporation, Lynn L Augspurger, Terrance A Meador, October 11, 1994: US05355460 (91 worldwide citation)

A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag ...


4
Bartholomew Blaner, Stamatis Vassiliadis: Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism. International Business Machines Corporation, Lynn L Augspurger, May 25, 1993: US05214763 (83 worldwide citation)

A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the ...


5
Bartholomew Blaner, Thomas L Jeremiah, Stamatis Vassiliadis, Phillip G Williams: Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit. International Business Machines Corporation, Lynn L Augspurger, February 15, 1994: US05287467 (82 worldwide citation)

The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detecte ...


6
Richard J Eickemeyer, Stamatis Vassiliadis: Method of indicating parallel execution compoundability of scalar instructions based on analysis of presumed instructions. International Business Machines Corporation, Lynn L Augspurger, Laurence J Marhoefer, Richard L Aitken, March 19, 1996: US05500942 (79 worldwide citation)

This is a method of compounding two or more instructions from an instruction stream without knowing the starting point or length of each individual instruction. All instructions include one OP Code at a predetermined field location which identifies the instruction and its length. Those instructions ...


7
James E Phillips, Bartholomew Blaner, Stamatis Vassiliadis: Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode. International Business Machines Corporation, Lynn L Augspurger, Laurence J Marhoefer, November 28, 1995: US05471628 (78 worldwide citation)

In a digital computer system both rotation of bits in a data byte and rotation in combination with additional manipulation, a multifunction permutation switch, in a cyclic mode of operation, connects the input bit lines to the output bit lines so that the sequence of input bits are maintained on the ...


8
Gerald G Pechanek, Stamatis Vassiliadis, Jose G Delgado Frias: Learning machine synapse processor system apparatus. International Business Machines, Eugene I Shkurko, Lynn L Augspurger, January 9, 1996: US05483620 (74 worldwide citation)

A Neural synapse processor apparatus having a neuron architecture for the synapse processing elements of the apparatus. The apparatus which we prefer will have a N neuron structure having synapse processing units that contain instruction and data storage units, receive instructions and data, and exe ...


9
James E Phillips, Bartholomew Blaner, Stamatis Vassiliadis: Status predictor for combined shifter-rotate/merge unit. International Business Machines Corporation, Lynn L Augspurger, Richard L Aitken, December 31, 1996: US05590348 (66 worldwide citation)

Generation of functional status followed by the use of the status to control the sequencing of microinstructions is a well known critical path in processor designs. The delay associated with the path is exacerbated in superscalar machines by the additional statuses that are produced by multiple func ...


10
Gerald George Pechanek, Stamatis Vassiliadis, Jose Guadalupe Delgado Frias: Massively parallel array processor. International Business Machines Corporation, John E Hoel Esq, Scott W Reid Esq, Morgan & Finnegan, June 11, 2002: US06405185 (66 worldwide citation)

Image processing for multimedia workstations is a computationally intensive task requiring special purpose hardware to meet the high speed requirements associated with the task. One type of specialized hardware that meets the computation high speed requirements is the mesh connected computer. Such a ...



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