1
Srinivasa R Malladi: Node loop port communication interface super core for fibre channel. LSI Logic Corporation, Henry K Woodward, Townsend and Townsend and Crew, January 28, 1997: US05598541 (153 worldwide citation)

A flexible architecture for the Super Core for implementing the FC-1 transmission protocol and the FC-2 signalling (framing) protocol in a 1.0625 Gbit/second Fibre Channel, which realizes 80 Mbytes/second sustained throughput. The architecture supports multiple, concurrent, open, and active exchange ...


2
Srinivasa R Malladi: Node loop core for implementing transmission protocol in fibre channel. LSI Logic Corporation, Henry K Woodward, Townsend and Townsend and Crew, June 10, 1997: US05638518 (122 worldwide citation)

Disclosed is a node loop port core for use in a Fibre Channel high speed data system for implementing transmission protocol and loop arbitration. The node loop core converts incoming data from 10 bit format to 8 bit format, checks frame CRC, parses frames, and steers the results to any one of a numb ...


3
Srinivasa R Malladi, Surya Varansi, Vanya Amla: MPEG decoder frame memory interface which is reconfigurable for different frame store architectures. LSI Logic Corporation, June 15, 1999: US05912676 (97 worldwide citation)

A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes ...


4
Srinivasa R Malladi, Marc A Miller, Kwok K Chau: Method for partitioning hardware and firmware tasks in digital audio/video decoding. LSI Logic Corporation, Hickman & Martine, September 29, 1998: US05815206 (52 worldwide citation)

Disclosed is a partitioning procedure for designing MPEG decoders, AC-3 decoders, and decoders for other audio/video standards. The procedure provides that some specified decoding functionality be implemented exclusively in the form of hardware and certain other specified decoding functionality be p ...


5
Srinivasa R Malladi, Venkat Mattela: Micro architecture of video core for MPEG-2 decoder. LSI Logic Corporation, Hickman & Martine, October 6, 1998: US05818532 (41 worldwide citation)

Disclosed is a reusable hardware layout ("core") for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit element ...


6
Srinivasa R Malladi: Method and apparatus for designing re-usable core interface shells. LSI Logic Corporation, Hickman & Martine, February 9, 1999: US05870310 (29 worldwide citation)

Disclosed is a method and apparatus for designing re-useable interfacing logic hardware shells which provide interface functions between a hardware core and one or more busses. An interface logic hardware shell provides previously characterized, tested and implemented interface logic designs for use ...


7
Jay Sethuram, Amir Nayyarhabibi, Chandra Shekhar Joshi, Rajiv Kane, Richard Joseph Weber, Srinivasa R Malladi: Method and apparatus for transceiving multiple services data simultaneously over SONET/SDH. Cisco Technology, Campbell Stephenson Ascolese, July 20, 2004: US06765928 (26 worldwide citation)

A method and apparatus for transceiving multiple service data from multiple communication services to a SONET/SDH communication system or network is provided. A SONET/SDH universal framer (SURF) bidirectionally provides communication between a SONET/SDH communication port and multiple service commun ...


8
Srinivasa R Malladi, Mahadev S Kolluru: Microarchitecture of audio core for an MPEG-2 and AC-3 decoder. LSI Logic Corporation, Hickman & Martine, December 1, 1998: US05845249 (18 worldwide citation)

A reusable hardware layout ("core") for performing some, but not all, MPEG and AC-3 audio decoding functions. Specifically, the audio core performs matrixing and windowing operations of MPEG and AC-3 decoding. The disclosed audio core design includes a data path, a control logic unit, an input RAM i ...


9
Srinivasa R Malladi, Venkat Mattela: Micro-architecture of video core for MPEG-2 decoder. LSI Logic Corporation, May 11, 1999: US05903312 (14 worldwide citation)

Disclosed is a reusable hardware layout ("core") for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit element ...


10
Srinivasa R Malladi, Venkat Mattela: Multiplier circuit for performing inverse quantization arithmetic. LSI Logic Corporation, B Noel Kivlin, Conley Rose & Tayon P C, July 21, 1998: US05784011 (8 worldwide citation)

An inverse quantizer includes a multiplier circuit using two adder/subtracter stages to perform a multiplication operation between the quantizer scale value and the weight value. The inverse quantizer may be employed within a video decoder circuit such an an MPEG decoder. The multiplier circuit incl ...