1
Kenneth C Creta, Robert G Blankenship, Sridhar Muthrasanallur, Jasmin Ajanovic: Transmitting peer-to-peer transactions through a coherent interface. Intel Corporation, Trop Pruner & Hu P C, April 24, 2007: US07210000 (33 worldwide citation)

In various embodiments, the present invention includes a method for receiving a transaction having first header information from a first peer device at a first agent of a coherent system, inserting second header information onto the transaction, and routing the transaction to a second peer device us ...


2
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Fallk, Avi, Ilan Pardo, Eran Tamari, Ellezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, May 24, 2011: US07949794 (32 worldwide citation)

A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Mess ...


3
Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M Bennett, Andrew V Anderson, Erik C Cota Robles: Delivering interrupts directly to a virtual processor. Intel Corporation, Trop Pruner & Hu P C, October 9, 2012: US08286162 (15 worldwide citation)

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the i ...


4
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions including transactions having prefetch parameters. Intel Corporation, David P McAbee, January 17, 2012: US08099523 (13 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


5
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, July 24, 2012: US08230120 (13 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


6
Justin Song, Devadatta V Bodas, Ohad Falik, Alon Naveh, Ilan Pardo, Anil Aggarwal, Sridhar Muthrasanallur, James B Crossland: Method, system, and apparatus for rerouting interrupts in a multi-core processor. Intel Corporation, Caven & Aghevli, June 14, 2011: US07962771 (13 worldwide citation)

A method, system, and apparatus may route an interrupt to a first core of a plurality of cores of a multi-core system. If the first core is in an idle or low power state, or operating in a power state at or below a threshold power state, a core in a least idle state may be found. The interrupt may b ...


7
Shivnandan D Kaushik, Keshavan K Tiruvallur, James B Crossland, Sridhar Muthrasanallur, Rajesh S Parthasarathy, Luke P Hood: Creation of logical APIC ID with cluster ID and intra-cluster ID. Intel Corporation, Alan K Aldous, December 1, 2009: US07627706 (11 worldwide citation)

In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identi ...


8
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, July 24, 2012: US08230119 (10 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


9
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, April 19, 2011: US07930566 (10 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...


10
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Avi, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, March 1, 2011: US07899943 (10 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...