1
James A Kahle, Soummya Mallick, Robert G McDonald, Edward L Swarthout: Method and system for executing a program within a multiscalar processor by processing linked thread descriptors. International Business Machines Corporation, Casimer K Salys, Felsman Bradley Vaden Gunter & Dillon, April 3, 2001: US06212542 (118 worldwide citation)

A multiscalar processor and method of executing a multiscalar program within a multiscalar processor having a plurality of processing elements and a thread scheduler are provided. The multiscalar program includes a plurality of threads that are each composed of one or more instructions of a selected ...


2
James Allan Kahle, Albert J Loper, Soummya Mallick, Aubrey Deene Ogden, John Victor Sell: Method and system for enhanced management operation utilizing intermixed user level and supervisory level instructions with partial concept synchronization. International Business Machines Corporation, Andrew J Dillon, June 9, 1998: US05764969 (98 worldwide citation)

A method and system for enhanced system management operations in a superscalar data processing system. Those supervisory level instructions which execute selected privileged operations within protected memory space are first identified as not requiring a full context synchronization. Each time execu ...


3
James A Kahle, Soummya Mallick, Robert G McDonald: Method and system for constructing a program including out-of-order threads and processor and method for executing threads out-of-order. International Business Machines Corporation, Michael A Davis Jr, Brian F Russell, Andrew J Dillon, June 22, 1999: US05913925 (96 worldwide citation)

A method and system for constructing a program are provided. According to the method, each of a plurality of instructions are assigned to at least one of a plurality of threads. The plurality of threads include first, second, and third threads, where the third thread follows the first thread and pre ...


4
Soummya Mallick, Robert G McDonald, Edward L Swarthout: Method and system for constructing a program including a navigation instruction. International Business Machines Corporation, Casimer K Salys, Brian F Russell, Andrew J Dillon, March 23, 1999: US05887166 (59 worldwide citation)

A method and system are provided for constructing a program executable by a processor including one or more processing elements for executing threads and a thread scheduler for assigning threads to the processing elements for execution. According to the method, a plurality of threads are provided th ...


5
Rajesh Bhikhubhai Patel, Soummya Mallick: Write-back cache having sub-line size coherency granularity and method for maintaining coherency within a write-back cache. International Business Machines Corporation, Brian F Russell, Andrew J Dillon, September 1, 1998: US05802572 (50 worldwide citation)

A write-back cache memory and method for maintaining coherency within a write-back cache memory are disclosed. The write-back cache memory includes a number of cache lines for storing data associated with addresses within an associated memory. Each of the cache lines comprises multiple byte sets. Th ...


6
Soummya Mallick, Robert G McDonald, Edward L Swarthout: Processor and method for dynamically inserting auxiliary instructions within an instruction stream during execution. International Business Machines Corporation, Casimer K Salys, Brian F Russell, Andrew J Dillon, October 5, 1999: US05961639 (44 worldwide citation)

A processor and method of executing a program within a processor are provided. According to the method, a plurality of program instructions comprising a program and a set of auxiliary instructions are stored. An instruction stream including selected ones of the plurality of program instructions is s ...


7
James A Kahle, Soummya Mallick, Robert G McDonald: Latency-based scheduling of instructions in a superscalar processor. International Business Machines Corporation, Casimer K Salys, Daniel E Venglarik, Andrew J Dillon, September 1, 1998: US05802386 (43 worldwide citation)

Instructions are efficiently scheduled for execution based on a stored identification of the first processor cycle when a result of a previous instruction required as an operand for the instruction to be scheduled will become available. Examination of stored processor cycle identifications for the o ...


8
Soummya Mallick: Address translation buffer for data processing system emulation mode. International Business Machines Corporation, Casimer K Salys, Brian F Russell, Andrew J Dillon, September 14, 1999: US05953520 (40 worldwide citation)

A processor and method of operating a processor which has a native instruction set and emulates instructions in a guest instruction set are described. According to the method, a series of guest instructions from the guest instruction set are stored in memory. The series includes a guest memory acces ...


9
Albert John Loper, Soummya Mallick: System and method for reducing power consumption in an electronic circuit. International Business Machines Corporation, Casimer K Salys, Michael Davis Jr, February 9, 1999: US05870616 (38 worldwide citation)

While a set-associative cache memory operates in a first power mode, information is stored in up to N number of ways of the cache memory, where N is an integer number and N>1. While the cache memory operates in a second power mode, the information is stored in up to M number of ways of the cache mem ...


10
James Allan Kahle, Soummya Mallick: Indirect unconditional branches in data processing system emulation mode. International Business Machines Corporation, Casimer K Salys, Brian F Russell, Andrew J Dillon, February 9, 1999: US05870575 (32 worldwide citation)

A processor and method of operating a processor which has a native instruction set and emulates guest instructions within a guest instruction set are described. According to the method, a series of guest instructions including at least one unconditional indirect guest branch instruction is stored in ...