1
Motti Beck, Ran Talmudi, Sorin Iacobovici: Processor with in-system emulation circuitry which uses the same group of terminals to output program counter bits. National Semiconductor Corporation, Limbach & Limbach, February 20, 1996: US05493723 (67 worldwide citation)

A processor emulation system for testing processor operation. First and second identical microprocessors are used together with a target system which includes the main memory. One microprocessor performs an in-system emulation (ISE) function by operating in lock step with the second processor which ...


2
Dean A Mulla, Sorin Iacobovici: Pending access queue for providing data to a target register during an intermediate pipeline phase after a computer cache miss. Hewlett Packard Company, Augustus W Winfield, February 6, 2001: US06185660 (56 worldwide citation)

An apparatus in a computer, called a pending access queue, for providing data for register load instructions after a cache miss. After a cache miss, when data is available for a register load instruction, the data is first directed to the pending access queue and is provided to an execution pipeline ...


3
Dean Mulla, Sorin Iacobovici: Cache arrangement including coalescing buffer queue for non-cacheable data. Institute for the Development of Emerging Architectures L L C, Jack A Lenell, September 2, 1997: US05664148 (48 worldwide citation)

An apparatus including a cache subsystem arrangement for efficient management of input/output operations and of memory shared by processors in a multiprocessor system. The apparatus includes a central processing unit, an input/output device such as a network device or a display device for example, a ...


4
Dean Mulla, Sorin Iacobovici: Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues. Institute for the Development of Emerging Architectures L L C, Jack A Lenell, July 29, 1997: US05652859 (47 worldwide citation)

A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least ...


5
Sorin Iacobovici, Daniel Leibholz, David J Greenhill: Versatile register file design for a multi-threaded processor utilizing different modes and register windows. Sun Microsystems, Osha Liang, August 26, 2008: US07418582 (44 worldwide citation)

A method for optimizing a register file hierarchy in a multithreaded processor. The method includes providing a register file hierarchy with a plurality of register file cells, associating the plurality of register file cells with respective threads when the processor is operating in a multithreaded ...


6
Sorin Iacobovici, William R Bryg, Joseph H Hassoun: Forming linked lists using content addressable memory. Hewlett Packard Company, November 30, 1999: US05995967 (15 worldwide citation)

A linked list structure in a computing system includes a first entry and additional entries. Each additional entry includes a link reference to a prior entry in the linked list. The link reference for each additional entry all are stored within a content addressable memory. Each additional entry is ...


7
Sorin Iacobovici, Ronald Melanson: Microprocessor speed control mechanism using power dissipation estimation based on the instruction data path. Sun Microsystems, Rosenthal & Osha L, March 9, 2004: US06704876 (15 worldwide citation)

A power dissipation control mechanism for a central processing unit includes a power estimation circuit for estimating the power dissipation of instructions executed by the central processing during a selected time interval and a speed controller for adjusting the speed of the central processing uni ...


8
Sorin Iacobovici: End-to-end residue based protection of an execution pipeline. Sun Microsystems, Osha • Liang, June 30, 2009: US07555692 (14 worldwide citation)

A processor that protects an execution pipeline includes a residue-based error detection infrastructure including a first logic for computing a first residue of a result of an executed instruction instance, and a second logic for computing a second residue of the result. The second logic applies ari ...


9
Sorin Iacobovici, Sudarshan Kadambi, Yuan C Chou: Multi-stride prefetcher with a recurring prefetch table. Sun Microsystems, Gunnison McKay & Hodgson L, Forrest Gunnison, February 3, 2009: US07487296 (12 worldwide citation)

A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also includes a thread number field to help support multi-threaded processor cores. The tag field stores a ...


10
Kenneth K Smith, Loren P Staley, Sorin Iacobovici: Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations. Hewlett Packard Company, April 25, 2000: US06055610 (12 worldwide citation)

A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In a ...