1
DongSoo Moon, Taewoo Lee, Soo San Park, SooMoon Park, Sang Ho Lee: Integrated circuit packaging system with interconnect and method of manufacture thereof. Stats Chippac, Mikio Ishimaru, February 14, 2012: US08115293 (15 worldwide citation)

A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting a component over the first substrate; mounting a stack substrate over the component, the stack substrate having an inner pad and an outer pad connected to the first substrate; mounting a ...


2
Chan Hoon Ko, Soo San Park, YoungChul Kim: Integrated circuit packaging system having dual sided connection and method of manufacture thereof. Stats Chippac, Mikio Ishimaru, April 12, 2011: US07923290 (13 worldwide citation)

A method of manufacture of an integrated circuit packaging system includes: mounting an integrated circuit, having a device through via and a device interconnect, over a substrate with the device through via traversing the integrated circuit and the device interconnect attached to the device through ...


3
Soo San Park, Gab Yong Min, Jin Wook Jeong, Hee Bong Lee, Jason Lee: System for peeling semiconductor chips from tape. Stats Chippac, Mikio Ishimaru, William D Zahrt II, July 3, 2007: US07238258 (10 worldwide citation)

A system for peeling semiconductor chips from tape is provided with a nose on a housing. The nose has transverse dimensions smaller than the transverse dimensions of a target chip. Apertures are provided through the nose from the housing. Vacuum ports are provided in the housing adjacent the nose. A ...


4
Soo San Park, Hyeog Chan Kwon, Sang Ho Lee, Jong Woo Ha: Integrated circuit package system including stacked die. Stats Chippac, Mikio Ishimaru, November 25, 2008: US07456088 (8 worldwide citation)

An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to ...


5
Jong Woo Ha, BumJoon Hong, Sang Ho Lee, Soo San Park: Integrated circuit package-in-package system with carrier interposer. Stats Chippac, Mikio Ishimaru, February 9, 2010: US07659609 (8 worldwide citation)

An integrated circuit package-in-package system includes: mounting an integrated circuit device over a package carrier; forming a subassembly including: providing an integrated circuit package system having a carrier interposer with an integrated circuit die thereover, and mounting a device under th ...


6
DaeSik Choi, BumJoon Hong, Sang Ho Lee, Jong Woo Ha, Soo San Park: Integrated circuit package system employing an offset stacked configuration. Stats Chippac, Mikio Ishimaru, January 18, 2011: US07872340 (5 worldwide citation)

A method for manufacturing an integrated circuit package system includes: providing a base package including a first integrated circuit coupled to a base substrate by an electrical interconnect formed on one side; and mounting an offset package over the base package, the offset package electrically ...


7
Soo San Park, Sang Ho Lee, DaeSik Choi: Integrated circuit packaging system with encapsulation and underfill and method of manufacture thereof. STATS ChipPAC, Ishimaru & Associates, Mikio Ishimaru, Stanley M Chang, September 25, 2012: US08273607 (5 worldwide citation)

A method of manufacture of an integrated circuit packaging system includes: providing a package carrier having a dispense port; attaching an integrated circuit to the package carrier and over the dispense port; placing a mold chase over the integrated circuit and on the package carrier, the mold cha ...


8
Soo San Park, Hyeog Chan Kwon, Sang Ho Lee, Jong Woo Ha: Integrated circuit package system including stacked die. Stats Chippac, Mikio Ishimaru, January 26, 2010: US07652376 (4 worldwide citation)

An integrated circuit package system is provided including providing a wafer with bond pads formed on the wafer. A solder bump is deposited on one or more bond pads. The bond pads and the solder bump are embedded within a mold compound formed on the wafer. A groove is formed in the mold compound to ...


9
Sang Ho Lee, Jong Woo Ha, Soo San Park: Integrated circuit package system with net spacer. Stats Chippac, Mikio Ishimaru, November 9, 2010: US07829986 (4 worldwide citation)

A method for manufacturing an integrated circuit package system is provided including: forming a strip level net spacer including support bars, tie bars and paddles; configuring the support bars, the tie bars and the paddles to form four or more open regions around each of the paddles; and interconn ...


10
Soo San Park: Integrated circuit package system with arched pedestal. Stats Chippac, Mikio Ishimaru, March 30, 2010: US07687919 (4 worldwide citation)

An integrated circuit package system includes an arched pedestal integrated circuit die including an active surface, a die mounting surface, a pedestal portion including an arch intersecting the die mounting surface and having an arch height, and the arch under a portion of the active surface and ha ...