1
Koji Matsuda, Soichi Takaya, Yoshihiro Miyazaki, Kenichi Kurosawa, Shinichiro Yamaguchi, Sako Ishikawa, Akira Yamagiwa, Masao Inoue, Kenji Kashiwagi: Uninterruptible clock supply apparatus for fault tolerant computer system. Hitachi, Kenyon & Kenyon, December 22, 1998: US05852728 (33 worldwide citation)

The present invention concerns clock source switchover between dual clock sources in the event of failure of any of them without affecting the clock output in the dual system, thereby preventing malfunctioning of processors therein. In the fault tolerant computer system of the invention, each of the ...


2
Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Takayuki Morioka, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki: Suspended instruction restart processing system based on a checkpoint microprogram address. Hitachi, Antonelli Terry Stout & Kraus, March 26, 1991: US05003458 (23 worldwide citation)

Method and apparatus for instruction restart processing in a microprogram - controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is ...


3
Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Morioka Takayuki, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki: System for storing restart address of microprogram, determining the validity, and using valid restart address to resume execution upon removal of suspension. Hitachi, Antonelli Terry Stout & Kraus, September 8, 1992: US05146569 (17 worldwide citation)

Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is s ...


4
Yoshihiro Miyazaki, Soichi Takaya, Masayuki Tanji, Atsuhiko Nishikawa, Shinichiro Yamaguchi: Method and apparatus for controlling interruption in the course of instruction execution in a processor. Hitachi, Antonelli Terry & Wands, August 16, 1988: US04764869 (12 worldwide citation)

Method and apparatus for controlling interruption of a processor. When an external interrupt request having a higher priority level than a current program level is detected in the course of the execution of an instruction, the processing is interrupted and an interexecution interruption is issued. T ...


5
Hiroshi Oguro, Shinichiro Yamaguchi, Yoshihiro Miyazaki, Soichi Takaya, Masataka Hiramatsu, Nobuo Akeura: Fault-tolerant computer system. Hitachi, Beall Law Offices, February 29, 2000: US06032265 (11 worldwide citation)

A fault-tolerant computer system, which prevents an I/O fault from reaching the CPU block while using an alternative I/O block to continue processing, employs common general-purpose processors with a minimum of specialized peripheral circuits. Dual system bus adapters are provided not in the fast-op ...


6
Atsuhiko Nishikawa, Yoshihiro Miyazaki, Masayuki Tanji, Soichi Takaya, Shinichiro Yamaguchi: Method for restarting execution interrupted due to page fault in a data processing system. Hitachi, Antonelli Terry & Wands, June 20, 1989: US04841439 (11 worldwide citation)

The present application invention relates to a method for restarting execution of an instruction interrupted due to a page fault. When a page fault occurs during an execution of an instruction, the pertinent page is loaded from an external storage into the main memory and then the access which has c ...


7
Soichi Takaya, Yoshihiro Miyazaki: Method for fast establishing a co-processor to memory linkage by main processor. Hitachi, Antonelli Terry Stout & Kraus, July 2, 1991: US05029073 (11 worldwide citation)

A co-processor control method intended to speed up data transfer linkage between the co-processor and memory when the co-processor is activated by the main processor, in such a way that the main processor issues an active control signal to the co-processor in the cycle of reading out an operand in t ...


8
Hiroaki Fukumaru, Soichi Takaya, Takayuki Morioka, Tadaaki Bandoh, Shinichiro Yamaguchi, Kenji Hirose: Operation control apparatus for a processor having a plurality of arithmetic devices. Hitachi, Hitachi Engineering, Antonelli Terry Stout & Kraus, October 30, 1990: US04967339 (10 worldwide citation)

A processor performs a pipelined parallel processing by an operand effective address calculation unit for calculating an operand effective address necessary to execute an instruction and an instruction execution unit for executing the instruction. A 64 bit width data operation is performed in such a ...


9
Yoshihiro Miyazaki, Yoshiaki Takahashi, Manabu Araoka, Soichi Takaya, Hiroaki Fukumaru: Method for controlling multiple common memories and multiple common memory system. Hitachi, Antonelli Terry Stout & Kraus, August 27, 1996: US05551007 (5 worldwide citation)

A multiple common memory system is provided in which at least three CPUs share at least two common memories each storing one and the same content. Each of the first and second CPUs contains a respective one of the two common memories, and each of the first and second CPUs has an arrangement to acces ...


10
Koji Matsuda, Yoshihiro Miyazaki, Soichi Takaya, Kazuhiro Hyuga, Nobuo Akeura, Shinichiro Yamaguchi, Naoto Miyazaki, Satoru Kayukawa: Method of and system for verifying operation concurrence in maintenance/replacement of twin CPUs. Hitachi, Hitachi Information & Control Systems, Kenyon & Kenyon, April 7, 1998: US05737513 (5 worldwide citation)

A method of verifying operation concurrence in maintenance/replacement of twin CPUs employed in a dual-CPU computer wherein a replacement CPU with an initial fault may have been installed by mistake during on-line maintenance/replacement work and a system therefor are disclosed whereby a failure whi ...