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Eb Eshun
Coolbaugh Douglas D, Eshun Ebenezer E, Rassel Robert M, Slinkman James A, Zierak Michael J: Semiconductor structure and its manufacturing method. Ibm, taofeng bei, May 7, 2008: CN200610136640

The present invention provides a method for fabricating high gain FETs which substantially reduces or eliminates unwanted variation in device characteristics caused by using a prior art shadow masking process is provided. The inventive method employs a blocking mask that at least partially extends o ...


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Juan A Chedeiakku, Randy W Mann, Slinkman James A: Semiconductor device and its manufacturing method. Internatl Business Mach Corp &Lt IBM&Gt, September 28, 2001: JP2001-267421 (2 worldwide citation)

PROBLEM TO BE SOLVED: To self-align to the gate structure of a field effect transistor, and prevent the occurrence of electric short-circuiting when a conductive stud is formed in a drain or source region.SOLUTION: On the surface of a semiconductor substrate 20, a gate dielectric 32, gate structure ...


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Ballantine Arne W, Ellis Monaghan John J, Furukawa Toshiharu, Glenn R Miller, Slinkman James A, Gilbert Jeffrey D: Dc or AC field assisted annealing. Internatl Business Mach Corp &Lt IBM&Gt, November 16, 2001: JP2001-319888 (1 worldwide citation)

PROBLEM TO BE SOLVED: To provide a method for forming a desired junction profile in a semiconductor device.SOLUTION: At least one dopant is thrown into a semiconductor substrate. At the same time, the semiconductor substrate and at least one dopant are annealed exposing the semiconductor substrate t ...


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Banke G William Jr, Deering Andrew, Kaszuba Philip V, Moszkowicz Leon, Robert James, Slinkman James A: Methods of measuring integrated circuit structure and preparation thereof. International Business Machines Corporation, Banke G William Jr, Deering Andrew, Kaszuba Philip V, Moszkowicz Leon, Robert James, Slinkman James A, SOUCAR Steven J, June 24, 2004: WO/2004/053928 (1 worldwide citation)

A method for measuring an integrated circuit (IC) structure (12) by measuring an imprint (30) of the structure, a method for preparing a test site (26) for the above measuring, and IC (10) so formed. The method for preparing the test site includes incrementally removing the structure from the substr ...


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BOTULA Alan B, JOSEPH Alvin J, SLINKMAN James A, WOLF Randy L: Procédé, appareil et structure de conception pour circuits à grande largeur de bande silicium sur isolant à couche de charge réduite, Method, apparatus, and design structure for silicon-on- insulator high-bandwidth circuitry with reduced charge layer. International Business Machines Corporation, BOTULA Alan B, JOSEPH Alvin J, SLINKMAN James A, WOLF Randy L, CAIN David A, February 9, 2012: WO/2012/018664 (1 worldwide citation)

A method, integrated circuit and design structure includes a silicon substrate layer (102) having trench structures (106) and an ion impurity implant (108). An insulator layer (110) is positioned on and contacts the silicon substrate layer. The insulator layer (110) fills the trench structures (106) ...


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BOTULA ALAN B, ELLIS MONAGHAN JOHN, JOSEPH ALVIN, LEVY MAX G, PHELPS RICHARD A, SLINKMAN JAMES A: [en] Silicon-on-insulator (SOI) structure configured for reduced harmonics, design structure and method. IBM, August 8, 2012: GB2487860-A

[en] Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relativel ...


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BOTULA ALAN B, JOSEPH ALVIN, SLINKMAN JAMES A, WOLF RANDY LEE: [en] Method, apparatus, and design structure for silicon-on-insulator high-bandwidth circuitry with reduced charge layer. IBM, April 10, 2013: GB2495464-A

[en] A method, integrated circuit and design structure includes a silicon substrate layer (102) having trench structures (106) and an ion impurity implant (108). An insulator layer (110) is positioned on and contacts the silicon substrate layer. The insulator layer (110) fills the trench structures ...


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Banke G William Jr, Deering Andrew, Kaszuba Philip V, Moszkowicz Leon, Robert James, Slinkman James A: Integrated circuit and methods of measurement and preparation of measurement structure. Ibm, September 7, 2005: EP1570514-A2

A method for measuring an integrated circuit (IC) structure (12) by measuring an imprint (30) of the structure, a method for preparing a test site (26) for the above measuring, and IC (10) so formed. The method for preparing the test site includes incrementally removing the structure from the substr ...


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Ballantine Arne W, Ellis Monaghan John, Furukawa Toshiharu, Miller Glenn R, Slinkman James A, Gilbert Jeffrey D: Method and device for electric field assisted anneal. Ibm, October 4, 2001: EP1139394-A2

A method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while simultaneous ...


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Botula Alan B, Joseph Alvin J, Nowak Edward J, Shi Yun, Slinkman James A: Semiconductor structure, forming and operating method thereof. Ibm, Qiu Jun, June 30, 2010: CN200910221772

A doped contact region having an opposite conductivity type as a bottom semiconductor layer is provided underneath a buried insulator layer in a bottom semiconductor layer. At least one conductive via structure extends from an interconnect-level metal line through a middle-of-line (MOL) dielectric l ...