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Simon C Watt: Write request interlock. Advanced RISC Machines, Albert C Smith, May 21, 1996: US05519854 (53 worldwide citation)

A CPU core 4 can operate at either an internal clock frequency fclk or an external clock frequency mclk. When operating at the internal clock frequency fclk, write request signals are buffered in a write buffer 10. When operating at the external clock frequency mclk, write request signals are unbuff ...


2
Simon C Watt: Synchronous/asynchronous feedback system having logic circuit for changing the state of the processing core in response to output of synchronous state machine and asynchronous late inputs. Advanced Risc Machines, Albert C Smith, John T McNelis, November 26, 1996: US05579526 (7 worldwide citation)

Data processing apparatus for executing successive data processing instructions comprises a processing core having a current operational state selected from a predetermined set of possible operational states, the current operational state being defined by a control state signal supplied to the core; ...