1
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, R Michael Ananian, Dorsey & Whitney, April 6, 2004: US06717576 (151 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphic ...


2
Jerome F Duluk Jr, Jack Benkual, Shun Wai Go, Sushma S Trivedi, Richard E Hessel, Joseph P Bratt: Graphics processor with pipeline state storage and retrieval. Apple Computer, Dorsey & Whitney, February 25, 2003: US06525737 (112 worldwide citation)

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon ...


3
Jerome F Duluk Jr, Jack Benkual, Vaughn T Arnold, Tuan D Nguyen, Richard E Hessel, Stephen L Dodgen, Shun Wai Go: Apparatus and method for geometry operations in a 3D-graphics pipeline. Apple Computer, R Michael Ananian, Dorsey & Whitney, June 10, 2003: US06577317 (82 worldwide citation)

An apparatus and methods for rendering 3D-graphics images preferably includes a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a geometry-operations pipeline, coupled to the port and to the output, the geometry-operations pipeline inc ...


4
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Ho, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple Computer, Dorsey & Whitney, January 23, 2007: US07167181 (68 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


5
Jerome F Duluk Jr, Jack Benkual, Shun Wai Go, Sushma S Trivedi, Richard E Hessel, Joseph P Bratt: Graphics processor with pipeline state storage and retrieval. Apple Computer, R Michael Ananian, Dorsey & Whitney, February 17, 2004: US06693639 (46 worldwide citation)

A deferred graphics pipeline processor comprised of a mode extraction unit and a Polygon Memory associated with the polygon unit. The mode extraction unit receives a data stream from a geometry unit and separates the data stream into vertices data, and non-vertices data which is sent to the Polygon ...


6
Guy Cote, Jeffrey E Frederiksen, Joseph P Bratt, Shun Wai Go, Timothy J Millet: Dual image sensor image processing system and method. Apple, Fletcher Yoder PC, July 23, 2013: US08493482 (33 worldwide citation)

Various techniques are provided for processing image data acquired using a digital image sensor. In accordance with aspects of the present disclosure, one such technique may relate to the processing of image data in a system that supports multiple image sensors. In one embodiment, the image processi ...


7
Kwong Tak A Chui, Shun Wai Go, Mark D Hayter, Chun H Ning, Amy K Silveria: Tracking a non-posted writes in a system using a storage location to store a write response indicator when the non-posted write has reached a target device. Broadcom Corporation, Garlick Harrison & Markison, February 21, 2006: US07003615 (27 worldwide citation)

An apparatus includes a storage location and a write monitor circuit coupled to the storage location. The storage location is configured to store a write response indicator which is capable of indicating a reception of at least one write response. Each write response indicates that a corresponding w ...


8
Jerome F Duluk Jr, Richard E Hessel, Vaughn T Arnold, Jack Benkual, Joseph P Bratt, George Cuan, Stephen L Dodgen, Emerson S Fang, Zhaoyu Gong, Thomas Y Yo, Hengwei Hsu, Sidong Li, Sam Ng, Matthew N Papakipos, Jason R Redgrave, Sushma S Trivedi, Nathan D Tuck, Shun Wai Go, Lindy Fung, Tuan D Nguyen, Joseph P Grass, Bo Hong, Abraham Mammen, Abbas Rashid, Albert Suan Wei Tsay: Deferred shading graphics pipeline processor having advanced features. Apple, Dorsey & Whitney, October 5, 2010: US07808503 (19 worldwide citation)

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphic ...


9
Chun Hung Ning, Laurent Rene Moll, Kwong Tak Chui, Shun Wai Go, Piyush Shashikant Jamkhandi: Programmable inter-virtual channel and intra-virtual channel instructions issuing rules for an I/O bus of a system-on-a-chip processor. Broadcom Corporation, Garlick Harrison & Markison, Bruce E Garlick, July 3, 2007: US07240141 (6 worldwide citation)

A method and apparatus for programming instruction issuing rules for instructions residing among various virtual channels, as well as the same virtual channel of an I/O bus interface for a system-on-a-chip processor. In the method and apparatus of the present invention both intra-virtual channel dep ...


10
D Amnon Silverstein, Shun Wai Go, Suk Hwan Lim, Timothy J Millet, Ting Chen, Bin Ni: Modeless video and still frame capture. Apple, Meyertons Hood Kivlin Kowert & Goetzel P C, Lawrence J Merkel, March 7, 2017: US09591219 (1 worldwide citation)

In an embodiment, an electronic device may be configured to capture still frames during video capture, but may capture the still frames in the 4×3 aspect ratio and at higher resolution than the 16×9 aspect ratio video frames. The device may interleave high resolution, 4×3 frames and lower resolution ...