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Shivaling S Mahant Shetti, Derek J Smith, Basavaraj I Pawate, George R Doddington, Warren L Bean, Mark G Harward, Thomas J Aton: Distributed processing memory chip with embedded logic having both data memory and broadcast memory. Texas Instruments Incorporated, Jacqueline J Garner, W James Brady III, Richard L Donaldson, May 12, 1998: US05751987 (200 worldwide citation)

Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data me ...


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Satwinder Malhi, Oh K Kwon, Shivaling S Mahant Shetti: Flip-chip test socket adaptor and method. Texas Instruments Incorporated, W James Brady III, Richard Donaldson, Melvin Sharp, December 17, 1991: US05073117 (131 worldwide citation)

A test set socket adaptor (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adaptor (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate fo ...


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Satwinder Malhi, Oh K Kwon, Shivaling S Mahant Shetti: Flip-chip test socket adaptor and method. Texas Instruments Incorporated, W James Brady III, James T Comfort, Melvin Sharp, April 9, 1991: US05006792 (130 worldwide citation)

A test set socket adapter (20) comprises a substrate (28), a plurality of cantilever beams (32) and a package (30). A bare chip (22) may be inserted into and held by the test socket adapter (20) for insertion into a standard test socket. The cantilevers (32) are designed to deflect and compensate fo ...


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Shivaling S Mahant Shetti, Thomas J Aton, Rebecca J Gale: Scanning electron microscope based parametric testing method and apparatus. Texas Instruments Incorporated, Ira S Matsil, B Peter Barndt, Richard L Donaldson, November 3, 1992: US05159752 (116 worldwide citation)

A scanning electron microscope (28) is connected to a test structure (48) formed on a semiconductor wafer. The test structure (48) comprises a plurality of first parallel structures (54) and a plurality of second parallel structure (56) transverse to and interlocking with the first structures (54). ...


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Ashwin H Shah, James D Gallia, I Fay Wang, Shivaling S Mahant Shetti: Memory with redundancy. Texas Instruments Incorporated, Robert Groover III, Douglas A Sorensen, Melvin Sharp, July 15, 1986: US04601019 (92 worldwide citation)

A byte-wide memory with column redundancy. The redundant columns can each be substituted for any column in the half-array, without regard to which bit position the defective column relates to. Fuses store the address information of the defective columns, and when a match between the externally recei ...


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Basavaraj Pawate, George Doddington, Shivaling S Mahant Shetti, Derek Smith: Apparatus, systems and methods for implementing memory embedded search arithmetic logic unit. Texas Instruments Incorporated, Mark A Valetti, W James Brady III, Richard L Donaldson, June 18, 1996: US05528550 (68 worldwide citation)

An active memory 14 is provided which includes a data memory 20 including rows and columns of storage locations for holding data. A broadcast memory 22 is provided which includes rows and columns of storage locations for holding control instructions. Search circuitry 26, 52 is provided which is oper ...


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Satwinder S Malhi, Ravishankar Sundaresan, Shivaling S Mahant Shetti: Elevated CMOS. Texas Instruments Incorporated, John D Crane, Richard L Donaldson, William E Hiller, March 8, 1994: US05293053 (43 worldwide citation)

A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ s ...


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Shivaling S Mahant Shetti, Aki Nishimura: Method and apparatus for measuring the capacitance of complementary field-effect transistor devices. Texas Instruments Incorporated, Stanton C Braden, James T Comfort, Melvin Sharp, January 3, 1989: US04795964 (24 worldwide citation)

A combination inverter chain and ring oscillator (200) is used to measure the capacitance of a field effect transistor device (12, 85, 202) by measuring the current associated with propagating a signal through the circuit at a certain signal frequency. Where the device (12) is a CMOS pair, the capac ...