1
Wai Fan Yau, David Cheung, Shin Puu Jeng, Kuowei Liu, Yung Cheng Yu: Low power method of depositing a low k dielectric with organo silane. Applied Materials, Thomason Moser & Patterson, June 6, 2000: US06072227 (247 worldwide citation)

A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas at a low RF power level from 20-200 W. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. ...


2
Wai Fan Yau, David Cheung, Shin Puu Jeng, Kuowei Liu, Yung Cheng Yu: Method of depositing a low k dielectric with organo silane. Applied Materials, Thomason Moser & Patterson, April 25, 2000: US06054379 (239 worldwide citation)

A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can a ...


3
Robert H Havemann, Shin puu Jeng: Multilevel interconnect structure with air gaps formed between metal leads. Texas Instruments Incorporated, Kay Houston, James Brady, Richard L Donaldson, October 24, 1995: US05461003 (208 worldwide citation)

A method for forming air gaps 22 between metal leads 16 of a semiconductor device and semiconductor device for same. A metal layer is deposited on a substrate 12. The metal layer is etched to form metal leads 16. A disposable solid layer 18 is deposited between the metal leads 16. A porous dielectri ...


4
Frederic Gaillard, Li Qun Xia, Tian Hoe Lim, Ellie Yieh, Wai Fan Yau, Shin Puu Jeng, Kuowei Liu, Yung Cheng Lu: Method of decreasing the K value in SiOC layer deposited by chemical vapor deposition. Applied Materials, Moser Patterson & Sheridan, September 30, 2003: US06627532 (185 worldwide citation)

A method for processing a substrate comprising depositing a dielectric layer comprising silicon, oxygen, and carbon on the substrate by chemical vapor deposition, wherein the dielectric layer has a carbon content of at least 1% by atomic weight and a dielectric constant of less than about 3, and dep ...


5
Farhad K Moghadam, David W Cheung, Ellie Yieh, Li Qun Xia, Wai Fan Yau, Chi I Lang, Shin Puu Jeng, Frederic Gaillard, Shankar Venkataraman, Srinivas Nemani: Formation of a liquid-like silica layer by reaction of an organosilicon compound and a hydroxyl forming compound. Applied Materials, Moser Patterson & Sheridan, July 2, 2002: US06413583 (156 worldwide citation)

A method for depositing silicon oxide layers having a low dielectric constant by reaction of an organosilicon compound and a hydroxyl forming compound at a substrate temperature less than about 400° C. The low dielectric constant films contain residual carbon and are useful for gap fill layers, pre- ...


6
David Cheung, Wai Fan Yau, Robert P Mandal, Shin Puu Jeng, Kuo Wei Liu, Yung Cheng Lu, Michael Barnes, Ralf B Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon: Plasma processes for depositing low dielectric constant films. Applied Materials, Thomason Moser & Patterson, October 16, 2001: US06303523 (150 worldwide citation)

A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10 W to about 200 W or a pulsed RF power level from about 20 W to about 500 W. Dissociation of the oxidizing gas can be increased ...


7
Chen Hua Yu, Jing Cheng Lin, Nai Wei Liu, Jui Pin Hung, Shin Puu Jeng: Interconnect structure for wafer level package. Taiwan Semiconductor Manufacturing Company, Slater and Matsil L, September 9, 2014: US08829676 (138 worldwide citation)

A package includes a device die having a substrate. A molding compound contacts a sidewall of the substrate. A metal pad is over the substrate. A passivation layer has a portion covering an edge portion of the metal pad. A metal pillar is over and contacting the metal pad. A dielectric layer is over ...


8
Hsien Wei Chen, Hao Yi Tsai, Hsueh Chung Chen, Shin Puu Jeng, Jian Hong Lin, Chih Tao Lin, Shih Hsun Hsu: Method and apparatus for enhanced CMP planarization using surrounded dummy design. Taiwan Semiconductor Manufacturing, Duane Morris, June 26, 2007: US07235424 (125 worldwide citation)

In one embodiment, the disclosure relates to a method and apparatus for inserting dummy patterns in sparsely populated portions of a metal layer. The dummy pattern counters the effects of variations of pattern density in a semiconductor layout which can cause uneven post-polish film thickness. An al ...


9
David Cheung, Wai Fan Yau, Robert P Mandal, Shin Puu Jeng, Kuo Wei Liu, Yung Cheng Lu, Michael Barnes, Ralf B Willecke, Farhad Moghadam, Tetsuya Ishikawa, Tze Wing Poon: Plasma processes for depositing low dielectric constant films. Applied Materials, Moser Patterson & Sheridan, December 9, 2003: US06660656 (92 worldwide citation)

A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10W to about 200W or a pulsed RF power level from about 20W to about 500W. Dissociation of the oxidizing gas can be increased pri ...


10
Robert H Havemann, Shin Puu Jeng, Bruce E Gnade, Chih Chen Cho: Method of making an interconnect structure with an integrated low density dielectric. Texas Instruments Incorporated, Richard A Stoltz, Richard L Donaldson, William E Hiller, January 30, 1996: US05488015 (77 worldwide citation)

This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applyi ...