1
Shigeto Mizukami: Semiconductor integrated circuit device with input-protecting circuit. Kabushiki Kaisha Toshiba, Loeb & Loeb, December 3, 1996: US05581103 (32 worldwide citation)

A semiconductor integrated circuit device, comprises: an n.sup.+ -type buried layer 12 formed on a surface of a p-type semiconductor substrate 11; an n-type semiconductor layer 71 formed on the n.sup.+ -type buried layer 12; a first p type well 16 formed in the semiconductor layer 71; a second p-typ ...


2
Takayuki Kawaguchi, Shigeto Mizukami, Yasumitsu Nozawa, Kouji Nakao: Semiconductor memory device having bit line equalizing means. Kabushiki Kaisha Toshiba, Foley & Lardner, January 23, 1996: US05487044 (18 worldwide citation)

A semiconductor memory device having memory cells arranged in a matrix, each of the memory cells having input/output terminals, word lines for selecting the memory cells, pairs of bit lines connected to the input/output terminals, bit line pulling-up means for pulling up the potential of the bit lin ...


3
Shigeto Mizukami, Makoto Segawa: Static random access memory. Kabushiki Kaisha Toshiba, Finnegan Henderson Farabow Garrett and Dunner, July 3, 1990: US04939691 (16 worldwide citation)

In a static random access memory, when data is written into said plurality of memory cells, a write enable signal is set at a low level, and after the data write is completed, the write enable signal is set at a high level. In response to a level change of the write enable signal from a low level to ...


4
Kouji Nakao, Shigeto Mizukami: Semiconductor memory device. Kabushiki Kaisha Toshiba, Spensley Horn Jubas & Lubitz, October 3, 1995: US05455795 (12 worldwide citation)

A semiconductor memory device comprises a page access mode, a plurality of sense amplifiers for detecting data read from a plurality of memory cells selected based on first address inputs A2 to An, a plurality of latch circuits for latching data from the plurality of sense amplifiers, a reading circ ...


5
Yasumitsu Nozawa, Shigeto Mizukami, Makoto Segawa: Semiconductor integrated circuit for a stable constant delay time. Kabushiki Kaisha Toshiba, Foley & Lardner, October 17, 1995: US05459423 (10 worldwide citation)

A delay circuit is interposed between first and second circuit systems both driven by a first supply voltage. The delay circuit delays a signal applied by the first circuit system, and then transmits the delayed signal to the second circuit system. In particular, a constant voltage supply circuit ge ...


6
Shoji Ariizumi, Makoto Segawa, Shigeto Mizukami: Random access memory with resistance to crystal lattice memory errors. Kabushiki Kaisha Toshiba, Finnegan Henderson Farabow Garrett and Dunner, July 26, 1988: US04760560 (5 worldwide citation)

A random access memory comprises a semiconductor body of one conductivity type, at least one first well region of an opposite conductivity type formed in the surface area of the semiconductor body, and a memory cell array having a plurality of memory cells formed in the first well region. A peripher ...