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Yuji Ozawa, Shigeshi Abiko, Frederic Boutaud: Address generating circuit for generating addresses separated by a prescribed step value in circular addressing. Texas Instruments Incorporated, Gerald E Laws, William B Kempler, Richard L Donaldson, June 9, 1998: US05765218 (20 worldwide citation)

An address generating circuit of simple configuration for circular addressing. A bit isolating circuit 304 extracts an index from an input address. When a step value input to an adder 302 is positive, an index generating circuit subtracts the sum of the index and step value from a block size of a me ...


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Shigeshi Abiko: Method of and circuit for generating bit-order modified binary signals. Texas Instruments Incorporated, William E Hiller, N Rhys Merrett, Melvin Sharp, May 16, 1989: US04831570 (16 worldwide citation)

A method of and a circuit for generating address signals, wherein a binary index signal and a binary base address signal are stored in index and address registers, respectively, whereupon the index signal and the base address signal are added together to produce an initial output address signal repr ...


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Yuji Ozawa, Shigeshi Abiko, Frederic Boutaud: Address generating circuit for block repeat addressing for a pipelined processor. Texas Instruments Incorporated, Gerald E Laws, William B Kempler, Richard L Donaldson, March 14, 2000: US06038649 (8 worldwide citation)

An address generating circuit of simple configuration for repeating a selected block of instructions is provided. An instruction address maintained by program counter 72 is compared to register 76 that holds the address of the end of the selected block of instructions. When the end address is detect ...


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Shigeshi Abiko, Shoji Saiki: Transversal filter circuit having tap circuits including bidirectional shift registers for serial multiplication. Texas Instruments Incorporated, William E Hiller, Richard L Donaldson, March 9, 1993: US05193070 (8 worldwide citation)

A transversal filter circuit including a plurality of tap circuits, each having a serial multiplication circuit having a simplified construction and not requiring a shift of decimal (binary) points of data during a partial product calculation and addition operation. The serial multiplier includes a ...


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Shigeshi Abiko, Shintaro Mizushima, Marc Couvrat: Arithmetic circuit. Texas Instruments Incorporated, Richard L Donaldson, William B Kempler, May 12, 1998: US05751618 (8 worldwide citation)

An arithmetic circuit is provided in which the circuit scale can be reduced and the circuit delay can be shortened. The upper 24 bits and lower 16 bits of the 40 bit data A and B, that is input into the arithmetic circuit 100, are calculated in the first arithmetic circuit 110 and the second arithme ...


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Hiroshi Takahashi, Shigeshi Abiko: Clock signal generating circuit. Texas Instruments Incorporated, Gerald E Laws, William B Kempler, Richard L Donaldson, October 6, 1998: US05818275

Clock signal generating circuit for preventing occurrence of clock skew, totally preventing through current, and readily controlling the clock, which includes a master clock signal generating circuit 2M and a slave clock signal generating circuit 2S. The master clock signal generating circuit 2M gen ...