1
Mark E Bauer, Steven Wells, David M Brown, Johnny Javanifard, Sherif Sweha, Robert N Hasbun, Gary J Gallagher, Mamun Rashid, Rodney R Rozman, Glen Hawk, George Blanchard, Mark Winston, Richard D Pashley: Method and circuitry for usage of partially functional nonvolatile memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 13, 1998: US05822256 (135 worldwide citation)

A method and circuitry are described that permit one to utilize a partially functional integrated circuit memory. A memory array is segregated into separate blocks that can each be isolated to minimize the amount of the memory array rendered unusable by a defect. Circuitry is also provided to progra ...


2
Sherif Sweha, Mark Bauer, Phil Kliza: Redundancy CAM using word line from memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 3, 1991: US05046046 (33 worldwide citation)

A redundancy programming circuit employing a two EPROM cell CAM for storing programmed states of redundant elements. The CAMs are disposed aside a memory array and word lines of the array are extended to the CAMs for programming the CAMs. Two word lines are coupled to each EPROM cell so that program ...


3
Sherif Sweha, Mark E Bauer: Bit map addressing schemes for flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 5, 1996: US05497354 (30 worldwide citation)

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected mem ...


4
Sherif Sweha, Mark E Bauer: Bit map addressing schemes for flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 19, 2002: US06483742 (21 worldwide citation)

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. “By-output” architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected mem ...


5
Sherif Sweha, Mark E Bauer: Bit map addressing schemes for flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 18, 1998: US05796667 (15 worldwide citation)

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected mem ...


6
Mark E Bauer, Peter Hazen, Sherif Sweha: High-speed tri-level decoder with dual-voltage isolation. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 28, 1993: US05274278 (12 worldwide citation)

In a memory array in which logic signals of a first and a second voltage levels are used for selecting memory positions in the array for read operations and at least one signal of a voltage level higher than the first and second voltage levels may appear, and including a plurality of wordlines each ...


7
Sherif Sweha, Mark E Bauer: Bit map addressing schemes for flash/memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 14, 1998: US05781472 (10 worldwide citation)

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected mem ...


8
Kevin W Frary, George Canepa, Sherif Sweha: Apparatus for increasing the speed of operation of non-volatile memory arrays. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 14, 1993: US05245574 (7 worldwide citation)

In a memory array having a plurality of bitlines each connected to a plurality of memory devices having a state in which current is transferred by the memory device and a state in which current is not transferred by the device, a column select device for activating each bitline, a plurality of wordl ...


9
Sherif Sweha, Mark E Bauer: Bit map addressing schemes for flash memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 29, 1998: US05815443 (6 worldwide citation)

Sense path and write path architectures for read and write accesses of a memory device having memory cells that store n binary bits are disclosed. "By-output" architectures provide one output per bit such that each selected memory cell is mapped to n outputs and the n bits stored in the selected mem ...


10
Peter Hazen, Sherif Sweha: Pre-decoding circuit and word line decoding circuit. Intel, September 22, 1994: JP1994-267281

PURPOSE: To increase the word line disconnection selection speed by using a powerful element, which can transfer a considerable quantity of current, as a P-channel element functioning as a switch which supplies a current with which a common node capacity is charged. CONSTITUTION: When both of input ...