1
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Sheldon Bernard Levenstein, Andrew Henry Wottreng: Thread switch control in a multithreaded processor system. International Business Machines Corporation, Karuna Ojanen, May 20, 2003: US06567839 (208 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


2
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Steven R Kunkel, Sheldon Bernard Levenstein, Andrew Henry Wottreng: Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, Birch Stewart Kolasch & Birch, August 15, 2000: US06105051 (69 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


3
David John Krolak, Sheldon Bernard Levenstein: Data processing system and multi-way set associative cache utilizing class predict data structure and method thereof. International Business Machines Corporation, Scott A Stinebruner, October 24, 2000: US06138209 (59 worldwide citation)

A data processing system and method thereof utilize a unique cache architecture that performs class prediction in a multi-way set associative cache during either or both of handling a memory access request by an anterior cache and translating a memory access request to an addressing format compatibl ...


4
Donald Lee Freerksen, Sheldon Bernard Levenstein, Gary Michael Lippert: Apparatus and method to improve performance of reads from and writes to shared memory locations. International Business Machines Corporation, Schmeiser Olsen & Watts, April 29, 2003: US06557084 (27 worldwide citation)

According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locat ...


5
John David Irish, Charles Luther Johnson, David John Krolak, Sheldon Bernard Levenstein: Pipelined memory interface and method for using the same. International Business Machines Corporation, Derek P Martin, August 4, 1998: US05790838 (13 worldwide citation)

According to the present invention, a pipelined SRAM structure and clocking method is disclosed. The SRAM interface and clocking method are specifically intended for use with Level 2 and Level 3 cache SRAM memory devices. In the present invention, the oscillator that generates the clock signal for t ...


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Michael Joseph Corrigan, Sheldon Bernard Levenstein, Terrence James Stewart: Pseudo-random address generation mechanism that reduces address translation time. International Business Machines Corporation, Steven W Roth, April 27, 1999: US05897662 (10 worldwide citation)

It is known that virtual memory segments that are allocated together tend to be used together. With existing sequential address allocation mechanisms, this in turn means that programs tend to end up using the same set or sets of virtual segment addresses (i.e., in the same minitable or minitables), ...


8
Sheldon Bernard Levenstein, Nghia Van Phan: Static adder using BICMOS emitter dot circuits. International Business Machines Corporation, Steven R Merchant Gould Smith Edell Welter & Schmidt Funk, September 22, 1998: US05812521 (4 worldwide citation)

A parallel static adder for adding two n-bit operands, the adder including half-sum circuitry, summing circuitry, and carry look-ahead circuitry. The half-sum circuitry receives a pair of same-order bits from the two n-bit operands, and generates a plurality of half-sum signals for each of the pairs ...


9
John Michael Borkenhagen, Richard James Eickemeyer, Sheldon Bernard Levenstein: Background completion of instruction and associated fetch request in multithread processor. International Business Machines, yu jing, July 29, 1998: CN97125461

The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The i ...


10
Donald Lee Freerksen, Sheldon Bernard Levenstein, Gary Michael Lippert: Apparatus and method to improve performance of reads from and writes to shared memory locations. Schmeiser Olsen & Watts, March 21, 2002: US20020035675-A1

According to the present invention, an apparatus and method for improving reads from and writes to shared memory locations is disclosed. By giving writes priority over reads, the current invention can decrease the time associated with certain sequences of reads from and writes to shared memory locat ...