1
Deva N Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo In Chen, Sharon Shi: Super trench MOSFET including buried source electrode and method of fabricating the same. Siliconix incorporated, Silicon Valley Patent Group, February 27, 2007: US07183610 (70 worldwide citation)

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes t ...


2
Deva N Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo In Chen, Sharon Shi: Super trench MOSFET including buried source electrode. Siliconix Incorporated, Patentability Associates, July 7, 2009: US07557409 (15 worldwide citation)

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes t ...


3
Deva N Pattanayak, Kyle Terrill, Sharon Shi, Misha Lee, Yuming Bai, Kam Lui, Kuo In Chen: Trench metal oxide semiconductor with recessed trench material and remote contacts. Vishay Siliconix, February 5, 2013: US08368126 (7 worldwide citation)

Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are emp ...


4
Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo In Chen, The Tu Chau, Sharon Shi, Qufei Chen: Super junction trench power MOSFET device fabrication. Vishay Siliconix, September 13, 2016: US09443974 (6 worldwide citation)

Methods of fabricating a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device are described. A column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant ...


5
Yang Gao, Kyle Terrill, Deva Pattanayak, Kuo In Chen, The Tu Chau, Sharon Shi, Qufei Chen: Super junction trench power MOSFET devices. Vishay Siliconix, August 23, 2016: US09425306 (6 worldwide citation)

In a super junction trench power MOSFET (metal oxide semiconductor field effect transistor) device, a column of p-type dopant in the super junction is separated from a first column of n-type dopant by a first column of oxide and from a second column of n-type dopant by a second column of oxide. In a ...


6
The Tu Chau, Sharon Shi, Qufei Chen, Martin Hernandez, Deva Pattanayak, Kyle Terrill, Kuo In Chen: Ultra-low drain-source resistance power MOSFET. Vishay Silconix, April 2, 2013: US08409954 (5 worldwide citation)

Ultra-low drain-source resistance power MOSFET. In accordance with an embodiment of the preset invention, a semiconductor device comprises a plurality of trench power MOSFETs. The plurality of trench power MOSFETs is formed in a second epitaxial layer. The second epitaxial layer is formed adjacent a ...


7
Deva N Pattanayak, Yuming Bai, Kyle Terrill, Christiana Yue, Robert Xu, Kam Hong Lui, Kuo In Chen, Sharon Shi: Method of fabricating super trench MOSFET including buried source electrode. Siliconix incorporated, Patentability Associates, April 27, 2010: US07704836 (2 worldwide citation)

In a trench MOSFET, the lower portion of the trench contains a buried source electrode, which is insulated from the epitaxial layer and semiconductor substrate but in electrical contact with the source region. When the MOSFET is in an “off” condition, the bias of the buried source electrode causes t ...


8
Robert Q Xu, Kuo In Chen, Karl Lichtenberger, Sharon Shi, Qufei Chen, Kyle Terrill: Super-high density trench MOSFET. Vishay Siliconix, August 30, 2016: US09431530 (1 worldwide citation)

A method, in one embodiment, can include forming a plurality of trenches in a body region for a vertical metal-oxide semiconductor field-effect transistor (MOSFET). In addition, the method can include angle implanting source regions into the body region. Furthermore, dielectric material can be grown ...


9
Qufei Chen, Kyle Terrill, Sharon Shi: MOSFET active area and edge termination area charge balance. VISHAY SILICONIX, November 1, 2016: US09484451 (1 worldwide citation)

A method for fabricating a MOSFET having an active area and an edge termination area is disclosed. The method includes forming a first plurality of implants at the bottom of trenches located in the active area and in the edge termination area. A second plurality of implants is formed at the bottom o ...


10
Yang Gao, Kuo In Chen, Kyle Terrill, Sharon Shi: Split gate semiconductor device with curved gate oxide profile. Vishay Siliconix, August 16, 2016: US09419129 (1 worldwide citation)

A split gate semiconductor device includes a trench gate having a first electrode region and a second electrode region that are separated from each other by a gate oxide layer and an adjacent dielectric layer. The boundary of the gate oxide layer and the dielectric layer is curved to avoid a sharp c ...