1
Debendra Das Sharma, Sharon M Ebner, John A Wickeraad, Joe P Cowan, Carl H Jackson: Apparatus and method for ensuring forward progress in coherent I/O systems. Hewlett Packard Development Company, Clare T Hartnett, October 21, 2003: US06636906 (37 worldwide citation)

A snapshot mechanism that includes an apparatus and method for tracking DMA read requests for cacheable data that can be altered before the data is returned to a requesting I/O device is herein disclosed. Attributes that uniquely identify the original I/O device and DMA read request are stored in a ...


2
Jeffrey C Swanson, Sharon M Ebner, John A Wickeraad: System and method for multiple cycle capture of chip state. Hewlett Packard Development Company, December 9, 2003: US06662313 (16 worldwide citation)

Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioni ...


3
Sharon M Ebner, John A Wickeraad: Systems and methods for prefetch operations to reduce latency associated with memory access. Hewlett Packard Development Company, April 6, 2004: US06718454 (14 worldwide citation)

A data processing system includes a memory storing data to be retrieved and an I/O controller configured to request data stored in the memory at a plurality of addresses. The I/O may be responsive to an internal or external device requesting such data. A fetch machine provides or initiates retrieval ...


4
Jeffrey C Swanson, Sharon M Ebner, John A Wickeraad: System and method for multiple cycle capture of chip state. Hewlett Packard Development Company, Fulbright & Jaworski, January 29, 2008: US07325164 (10 worldwide citation)

Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to ...


5
Debendra Das Sharma, Sharon M Ebner, John A Wickeraad, Joe P Cowan, Carl H Jackson: Using read current transactions for improved performance in directory-based coherent I/O systems. Hewlett Packard Development Company, November 11, 2003: US06647469 (10 worldwide citation)

A shared memory provides data access to a plurality of agents (e.g., processor, cells of processors, I/O controllers, etc.) and includes a memory and a memory controller. The memory controller selectively provides memory access to the agents in both coherent and read current modes of operation. In t ...


6
Sharon M Ebner, Debendra Das Sharma: Arbitration scheme for equitable distribution of bandwidth for agents with different bandwidth requirements. Hewlett Packard Development Company, July 15, 2003: US06594718 (10 worldwide citation)

A device for arbitrating access to a resource by a plurality of agents includes logic configured to associate requesting ones of the agents with access tokens. The number of the access tokens assigned to each requesting agent is proportional to its bandwidth or speed in comparison with the other req ...


7
Sharon M Ebner, John A Wickeraad: Per cache line semaphore for cache access arbitration. Hewlett Packard Development Company, August 9, 2005: US06928525 (9 worldwide citation)

A semaphore mechanism in a multiport cache memory system allows concurrent accesses to the cache memory. When there is no contention for the same cache line, multiple requesters may access the cache memory concurrently. A status bit in each cache line indicates whether that particular cache line is ...


8
Jeffrey C Swanson, Sharon M Ebner, John A Wickeraad: System and method for multiple cycle capture of chip state. Hewlett Packard Company, August 5, 2004: US20040153838-A1

Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A test device includes a state machine responsive to (i) an arm command for transitioni ...


9
Sharon M Ebner: Method, apparatus, and system for processing a plurality of outstanding data requests. Hewlett Packard Company, September 30, 2004: US20040193771-A1

A method, apparatus, and system for processing a plurality of outstanding data requests from an expansion device connected to a computer system. The processing of one data request may commence before a previous request has been fully processed. Multiple data requests may be fetched from the computer ...


10
Sharon M Ebner, John A Wickeraad: Cache status data structure. Hewlett Packard Company, June 5, 2003: US20030105929-A1

A cache status data structure in a cache memory system provides a large amount of status data, which various requesters, e.g., processors and I/O devices, may read, modify and/or write to, in order to allows flexibility in the manner in which the various requesters access the cache memory. The cache ...