1
Oleg Siniaguine, Sergey Savastiouk: Package of integrated circuits and vertical integration. Tru Si Technologies, Michael Shenker, Skjerven Morrill MacPherson, November 27, 2001: US06322903 (472 worldwide citation)

A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the via ...


2
Sergey Savastiouk, Patrick B Halahan, Sam Kao: Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, May 23, 2006: US07049170 (285 worldwide citation)

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circui ...


3
Oleg Siniaguine, Sergey Savastiouk: Packaging of integrated circuits and vertical integration. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, February 17, 2004: US06693361 (268 worldwide citation)

A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the via ...


4
Sergey Savastiouk, Patrick B Halahan, Sam Kao: Packaging substrates for integrated circuits and soldering methods. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, June 13, 2006: US07060601 (264 worldwide citation)

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circui ...


5
Patrick A Halahan, Sam Kao, Bosco Lan, Sergey Savastiouk, Oleg Siniaguine: Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, May 24, 2005: US06897148 (78 worldwide citation)

A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into t ...


6
Sergey Savastiouk, Patrick B Halahan, Sam Kao: Packaging substrates for integrated circuits and soldering methods. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, April 25, 2006: US07034401 (71 worldwide citation)

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circui ...


7
Oleg Siniaguine, Patrick B Halahan, Sergey Savastiouk: Thinning and dicing of semiconductor wafers using dry etch, and obtaining semiconductor chips with rounded bottom edges and corners. Tru Si Technologies, Michael Shenker, Skjerven Morrill, December 24, 2002: US06498074 (53 worldwide citation)

A semiconductor wafer is diced before thinning. The wafer is diced only part of the way through, to form grooves which are at least as deep as the final thickness of each chip to be obtained from the wafer. Then the wafer backside is etched with a dry etch, for example, atmospheric pressure plasma e ...


8
Sergey Savastiouk, Sam Kao: Attachment of integrated circuit structures and other substrates to substrates with vias. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, July 10, 2007: US07241641 (44 worldwide citation)

Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong ...


9
Sergey Savastiouk, Sam Kao: Attachment of integrated circuit structures and other substrates to substrates with vias. Tru Si Technologies, MacPherson Kwok Chen & Heid, Michael Shenker, July 10, 2007: US07241675 (42 worldwide citation)

Vias (210, 210B) are formed in a surface of a substrate. At least portions of contact pads (139, 350) are located in the vias. Contact pads (150, 340) of an integrated circuit structure are inserted into the vias and attached to the contact pads (139, 350) of the substrate. The vias provide a strong ...


10
Sergey Savastiouk, Patrick B Halahan, Sam Kao: Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, March 6, 2007: US07186586 (40 worldwide citation)

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circui ...