1
Yasumitsu Murai, Hisashi Iwamoto, Yasuhiro Konishi, Naoya Watanabe, Seiji Sawada: Synchronous type semiconductor memory device operating in synchronization with an external clock signal. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, Lowe Price LeBlanc & Becker, April 4, 1995: US05404338 (127 worldwide citation)

In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in ...


2
Yasuhiro Konishi, Hisashi Iwamoto, Takashi Araki, Yasumitsu Murai, Seiji Sawada: Synchronous semiconductor memory device and synchronous memory module. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, McDermott Will & Emery, September 29, 1998: US05815462 (96 worldwide citation)

A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and ...


3
Sunao Satake, Seiji Sawada, Yasuharu Iida, Tsutomu Fujigamori: Ink jet recording liquid. Toyo Ink Manufacturing, Oblon Spivak McClelland Maier & Neustadt P C, September 29, 1998: US05814685 (66 worldwide citation)

The present invention relates to an aqueous ink jet recording liquid of a pigment type, which liquid has excellent stability and printing characteristics; and also to a process for the preparation of said liquid. The ink jet recording liquid of the present invention is obtained by dispersing a pigme ...


4
Seiji Sawada, Yasuhiro Konishi: Test circuit in clock synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price Leblanc & Becker, December 24, 1996: US05587950 (53 worldwide citation)

In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression c ...


5
Seiji Sawada, Yasuhiro Konishi: Test circuit for refresh counter of clock synchronous type semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, November 28, 1995: US05471430 (52 worldwide citation)

A synchronous semiconductor memory device includes an automatic refresh detection circuit for detecting that an automatic refresh mode is specified in accordance with an automatic refresh command, an address counter for generating a refresh address, a refresh execution unit for refreshing a memory a ...


6
Hisashi Iwamoto, Yasumitsu Murai, Yasuhiro Konishi, Naoya Watanabe, Seiji Sawada: Synchronous type semiconductor memory device operating in synchronization with an external clock signal. Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric Engineering, Lowe Price LeBlanc & Becker, May 14, 1996: US05517462 (49 worldwide citation)

In a synchronous semiconductor memory device, memory arrays (MA) forming activation units each are divided into a plurality of small memory arrays (MK). There are provided local I/O line pairs (LIO) each for two small memory arrays. The global I/O line pairs (GIO) crossing word lines are arranged in ...


7
Seiji Sawada, Yasuhiro Konishi: Test circuit in clock synchronous semiconductor memory device. Mitsubishi Denki Kabushiki Kaisha, Lowe Price LeBlanc & Becker, April 23, 1996: US05511029 (48 worldwide citation)

In order to reduce a test time for a synchronous type memory device, a compression circuit compresses a plurality of memory cell data which are inputted in a plurality of read registers provided for a data output terminal to 1-bit data. A bank selection circuit selects an output of the compression c ...


8
Seiji Sawada: Synchronous semiconductor memory device with auto precharge operation easily controlled. Mitsubishi Denki Kabushiki Kaisha, McDermott Will & Emery, May 5, 1998: US05748560 (40 worldwide citation)

An internal read/write termination detect circuit generates a one shot pulse signal when a read operation activation signal and a write operation activation signal are both set to an inactive state. An internal operation activation signal generation circuit holds an auto precharge enable signal by a ...


9
Seiji Aida, Tsutomu Fujigamori, Hisashi Uraki, Ichiro Toyoda, Sunao Satake, Seiji Sawada, Yasuharu Iida: Recording fluid for ink-jet printing and process for the production thereof. Toyo Ink Manufacturing, Wenderoth Lind & Ponack, February 10, 1998: US05716435 (34 worldwide citation)

A water-dispersed inkjet recording liquid excellent in water resistance and transparency and also excellent in the property of ejection from a nozzle, containing, as a colorant, a water-based dispersion of an organic pigment (A) having an average particle diameter of 10 to 150 nm (measured by laser ...


10
Yukiko Maruyama, Seiji Sawada: Synchronous semiconductor memory device performing data output in synchronization with external clock. Mitsubishi Denki Kabushiki Kaisha, McDermott Will & Emery, July 30, 2002: US06426900 (29 worldwide citation)

A DLL circuit generates a control clock specifying an operating timing of a data output buffer according to an external clock. The DLL circuit includes a replica delay time adjusting section and a phase control section. The phase control section controls such that a feedback clock and the external c ...



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