1
Scott T Becker, Michael C Smayling: Dynamic array architecture. Tela Innovations, Martine Penilla Gencarella, November 4, 2008: US07446352 (201 worldwide citation)

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over t ...


2
Scott T Becker, Michael C Smayling: Integrated circuit having gate electrode level region including at least four linear-shaped conductive structures with some outer-contacted linear-shaped conductive structures having larger outer extending portion than inner extending portion. Tela Innovations, Martine Penilla Group, March 13, 2012: US08134184 (137 worldwide citation)

A layout of a cell of a semiconductor device is disclosed to include a diffusion level layout including a plurality of diffusion region layout shapes, including a p-type and an n-type diffusion region separated by a central inactive region. The layout of the cell includes a gate electrode level layo ...


3
Scott T Becker, Michael C Smayling: Methods for defining dynamic array section with manufacturing assurance halo and apparatus implementing the same. Tela Innovations, Martine Penilla & Gencarella, February 15, 2011: US07888705 (128 worldwide citation)

A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. ...


4
Scott T Becker, Michael C Smayling: Semiconductor device with dynamic array section. Tela Innovations, Martine Penilla, Gencarella, March 29, 2011: US07917879 (126 worldwide citation)

A semiconductor chip is provided to include one or more distinct but functionally interfaced dynamic array sections. Each dynamic array section follows a dynamic array architecture that requires conductive features to be linearly defined along a virtual grate in each of a plurality of levels of the ...


5
Scott T Becker, Michael C Smayling: Semiconductor device having at least three linear-shaped electrode level conductive features of equal length positioned side-by-side at equal pitch. Tela Innovations, Martine Penilla Group, November 15, 2011: US08058671 (125 worldwide citation)

A semiconductor device includes a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive feature ...


6
Scott T Becker, Michael C Smayling: Semiconductor device and associated layouts including gate electrode level region having arrangement of six linear conductive segments with side-to-side spacing less than 360 nanometers. Tela Innovations, Martine Penilla & Gencarella, April 26, 2011: US07932545 (125 worldwide citation)

A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of cond ...


7
Scott T Becker, Michael C Smayling: Dynamic array architecture. Tela Innovations, Martine Penilla & Gencarella, November 30, 2010: US07842975 (125 worldwide citation)

A semiconductor device includes a substrate portion and a number of diffusion regions defined within the substrate portion. The diffusion regions are separated from each other by a non-active region of the substrate portion. The semiconductor device includes a number of linear gate electrode segment ...


8
Scott T Becker, Michael C Smayling: Semiconductor device and associated layouts having transistors formed from linear conductive segment with non-active neighboring linear conductive segment. Tela Innovations, Martine Penilla & Gencarella, March 22, 2011: US07910958 (124 worldwide citation)

A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of cond ...


9
Scott T Becker, Michael C Smayling: Methods for designing semiconductor device with dynamic array section. Tela Innovations, Martine Penilla & Gencarella, March 15, 2011: US07908578 (124 worldwide citation)

A method is provided for designing a semiconductor chip having one or more functionally interfaced dynamic array sections. A virtual grate is laid out for conductive features used to define a gate electrode level of a dynamic array section. The virtual grate is defined by a framework of parallel lin ...


10
Scott T Becker: Cross-coupled transistor layouts in restricted gate level layout architecture. Tela Innovations, Martine Penilla & Gencarella, June 7, 2011: US07956421 (101 worldwide citation)

A first P channel transistor and a first N channel transistor are defined by first and second gate electrodes, respectively. The second gate electrode is electrically connected to the first gate electrode. A second P channel transistor and a second N channel transistor are defined by third and fourt ...