1
Scott Luning, David Wu, Khanh Tran: Low-K sub spacer pocket formation for gate capacitance reduction. Advanced Micro Devices, February 26, 2002: US06351013 (127 worldwide citation)

The capacitance between the gate electrode and the source/drain regions of a semiconductor device is reduced by forming sub-spacers of a low dielectric constant (K) material at the corners of the gate electrode above the source/drain regions. Subsequently, insulating sidewall spacers are formed over ...


2
Andrew M Waite, Scott Luning: Integrated circuit and method for its manufacture. Advanced Micro Devices, Ingrassia Fisher & Lorenz P C, December 6, 2005: US06972478 (118 worldwide citation)

An integrated circuit and methods for its manufacture are provided. The integrated circuit comprises a bulk silicon substrate having a first region of crystalline orientation and a second region of crystalline orientation. A layer of silicon on insulator overlies a portion of the bulk silicon substr ...


3
Ralf van Bentum, Scott Luning, Andy Wei: Advanced technique for forming a transistor having raised drain and source regions. Advanced Micro Devices, Williams Morgan & Amerson P C, November 21, 2006: US07138320 (52 worldwide citation)

By recessing a semiconductor layer, preferably by locally oxidizing the semiconductor layer, a stress-inducing material and/or a dopant species may be introduced into the thinned semiconductor layer in the vicinity of a gate electrode structure by means of a subsequent epitaxial growth process. In p ...


4
Richard K Klein, Darrell Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming Ren Lin: Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device. Advanced Micro Devices, Foley & Lardner, June 23, 1998: US05770519 (27 worldwide citation)

A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A b ...


5
David Wu, Scott Luning: CMOS semiconductor device comprising graded junctions with reduced junction capacitance. Advanced Micro Devices, August 22, 2000: US06107149 (26 worldwide citation)

A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with ...


6
Massud Aminpur, David Wu, Scott Luning: Control trimming of hard mask for sub-100 nanometer transistor gate. Advanced Micro Devices, Williams Morgan & Amerson P C, November 19, 2002: US06482726 (26 worldwide citation)

A method is provided, the method including forming a gate dielectric layer above a substrate layer, forming a gate conductor layer above the gate dielectric layer, forming a first hard mask layer above the gate conductor layer, and forming a second hard mask layer above the first hard mask layer. Th ...


7
Scott Luning, Roger Alvis: Self-aligned implant energy modulation for shallow source drain extension formation. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, July 22, 1997: US05650343 (24 worldwide citation)

A process for forming shallow and/or lightly doped regions of impurity concentration adjacent to source/drain semiconductor regions in a semiconductor device. In one embodiment, the invention comprises: (a) providing a semiconductor of a first conductivity type having a first surface; (b) forming a ...


8
Bin Yu, Emi Ishida, Scott Luning, Timothy Thurgate: Very low thermal budget channel implant process for semiconductors. Advanced Micro Devices, Mikio Ishimaru, January 30, 2001: US06180468 (20 worldwide citation)

An ultra-low thermal budget process is provided for channel implant by using a reverse process sequence where a conventional MOS transistor is formed without the channel implant. The originally deposited polysilicon gate is removed, a nitride film deposition and etch is used to form a nitride spacer ...


9
Jian Chen, Yuan Tang, Scott Luning, Salvatore F Cagnina: Method of making flash EEPROM memory with reduced column leakage current. Advanced Micro Devices, Michael A Lechter, January 9, 1996: US05482881 (18 worldwide citation)

A flash EEPROM having reduced column leakage current suitably includes cells with more uniform erase times arranged in an array. An intermediate n+ implant immediately following the DDI implant step suitably provides an enhanced doping profile in the tunneling region, which increases the rate at whi ...


10
Ralf van Bentum, Scott Luning, Thorsten Kammler: Technique for forming transistors having raised drain and source regions with different heights. Advanced Micro Devices, Williams Morgan & Amerson P C, February 13, 2007: US07176110 (14 worldwide citation)

The height of epitaxially grown semiconductor regions in extremely scaled semiconductor devices may be adjusted individually for different device regions in that two or more epitaxial growth steps may be carried out, wherein an epitaxial growth mask selectively suppresses the formation of a semicond ...