1
Isaiah Oladeji
Isaiah O Oladeji, Scott Jessen, Joseph Ashley Taylor: Mask layer and interconnect structure for dual damascene semiconductor manufacturing. Beusse Brownlee Bowdoin & Wolter P A, April 3, 2003: US20030064582-A1 (1 worldwide citation)

A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over t ...


2
Isaiah Oladeji
Isaiah O Oladeji, Scott Jessen, Joseph Ashley Taylor: Mask layer and interconnect structure for dual damascene semiconductor manufacturing. Beusse Brownlee Wolter Mora & Maire P A, September 2, 2004: US20040171256-A1

A novel mask layer is used in the dual damascene construction of an interconnect structure of an integrated circuit device. The interconnect structure has a low-k dielectric material. The mask layer has a passivation film deposited on the low-k dielectric material, a barrier film is deposited over t ...


3
Isaiah Oladeji
Robert Y S Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O Oladeji, Kurt Geroge Steiner, Joseph Ashley Taylor: Mask layer and dual damascene interconnect structure in a semiconductor device. James H Beusse Esquire, Beusse Brownlee Bowdoin & Wolter Pa, June 26, 2003: US20030119305-A1

A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that o ...


4
Isaiah Oladeji
Robert YS Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O Oladeji, Kurt Geroge Steiner, Joseph Ashley Taylor: Mask layer and dual damascene interconnect structure in a semiconductor device. Beusse Brownlee Wolter Mora & Maire P A, June 24, 2004: US20040121579-A1

A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that o ...


5
Scott Jessen, John Martin McIntosh, Scott M Nagel: Substrate topography compensation at mask design: 3D OPC topography anchored. Agere Systems, May 17, 2005: US06893800 (37 worldwide citation)

A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the ...


6
James W Blatchford, Scott Jessen, Brittin C Kane, Nace Layadi, John M McIntosh, Simon J Molloy: Method analyzing a semiconductor surface using line width metrology with auto-correlation operation. Agere Systems Guardian, Allen Dyer Doppelt Milbrath & Gilchrist P A, July 10, 2001: US06258610 (23 worldwide citation)

A method for analyzing a semiconductor surface having patterned features on the surface is disclosed. At least one patterned feature is scanned to produce a scanned waveform signal having signal segments corresponding to characteristic surface portions of the patterned feature. The signal segments a ...


7
Thomas E Adams, Thomas S Frederick, Scott Jessen, John M McIntosh, Catherine Vartuli: Method of monitoring a patterned transfer process using line width metrology. Agere Systems Guardian, Allen Dyer Doppelt Milbrah & Gilchrist P A, May 1, 2001: US06225639 (17 worldwide citation)

A patterned transfer process in the manufacture of a semiconductor device is monitored. Patterned features formed on a semiconductor layer to be etched are scanned for generating a first amplitude modulated waveform intensity signal. The first amplitude modulated waveform intensity signal is sampled ...


8
Kurt G Steiner, Susan Vitkavage, Steve Lytle, Gerald Gibson, Scott Jessen: Structure and method for isolating porous low-k dielectric films. Agere Systems, James H Beusse, Beusse Brownlee Wolter Mora & Maire P A, September 28, 2004: US06798043 (10 worldwide citation)

A film structure includes low-k dielectric films and N—H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N—H base film is a TEOS oxide film which suppresses the diffusion of amines or other N—H bases from th ...


9
Gerald W Gibson Jr, Scott Jessen, Steven Alan Lytle, Kurt George Steiner, Susan Clay Vitkavage: Split barrier layer including nitrogen-containing portion and oxygen-containing portion. Agere Systems, April 12, 2005: US06879046 (7 worldwide citation)

A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N—H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielect ...


10
Robert Y S Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O Oladeji, Kurt George Steiner, Joseph Ashley Taylor: Mask layer and dual damascene interconnect structure in a semiconductor device. Agere Systems, June 27, 2006: US07067419 (5 worldwide citation)

A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that o ...



Click the thumbnails below to visualize the patent trend.