31
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, March 29, 2016: US09298641

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


32
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, May 3, 2016: US09330021

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


33
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Nicholson De Vos Webster & Elliott, June 21, 2016: US09372806

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


34
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Nicholson De Vos Webster & Elliott, June 21, 2016: US09372807

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


35
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard A Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, June 13, 2017: US09678890

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


36
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Mnemoglyphics, Lawrence M Mennemeier, September 22, 2015: US09141555

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


37
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Richard Uhlig, Scott Dion Rodgers, Rajesh M Sankaran, Camron Rust, Sebastian Schoenberg: Synchronizing a translation lookaside buffer with an extended paging table. Intel Corporation, Nicholson De Vos Webster & Elliot, January 15, 2019: US10180911

A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookas ...


38
Baiju V Patel, Rajeev Gopalakrishna, Andrew F Glew, Robert J Kushlis, Don Alan Van Dyke, Joseph Frank Cihula, Asit K Mallick, James B Crossland, Gilbert Neiger, Scott Dion Rodgers, Martin Guy Dixon, Mark Jay Charney, Jacob: Managing and implementing metadata in central processing unit using register extensions. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 21, 2014: US08635415

A set of default registers of a processor are expanded into metadata registers on the processor of a computer system. The default registers having stored thereon data, while metadata which is related to the data is stored separately on the metadata registers.


39
Hong Wang, Gautham N Chinya, Richard A Hankins, Shivnandan D Kaushik, Bryant Bigbee, Per Hammarlund, Xiang Zou, Jason W Brandt, Prashant Sethi, Douglas M Carmean, Baiju V Patel, John Shen, Scott Dion Rodgers, Ryan N Rakvic, John L Reid, David K Poulsen, Sanjiv M Shah, James Paul Held, James Charles Abel: Sequencer address management. Blakely Sokoloff Taylor & Zafman, October 5, 2006: US20060224858-A1

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses ...


40
Xiang Zou, Hong Wang, Scott Dion Rodgers, Darrell D Boggs, Bryant Bigbee, Shivanandan Kaushik, Anil Aggarwal, Ittai Anati, Doron Orenstein, Per Hammarlund, John Shen, Larry O Smith, James B Crossland, Chris J Newburn: Programmable event driven yield mechanism which may activate service threads. Blakely Sokoloff Taylor & Zafman, December 28, 2006: US20060294347-A1

Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be ...