1
Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki, Shigeru Takahashi, Atsushi Hiraishi, Yutaka Kobayashi, Seigou Yukutake: SRAM having load transistor formed above driver transistor. Hitachi, Antonelli Terry Stout & Kraus, November 10, 1998: US05834851 (158 worldwide citation)

Herein disclosed is a semiconductor integrated circuit device comprising a SRAM having its memory cell composed of transfer MISFETs to be controlled through word lines and drive MISFETs. The gate electrodes of the drive MISFETs and the gate electrodes of the transfer MISFETs of the memory cell, and ...


2
Masaaki Aoki, Toshiaki Masuhara, Terunori Warabisako, Shoji Hanamura, Yoshio Sakai, Seiichi Isomae, Satoshi Meguro, Shuji Ikeda: Recrystallized CMOS with different crystal planes. Hitachi, Antonelli Terry & Wands, August 30, 1988: US04768076 (94 worldwide citation)

A CMOS IC is formed on a semiconductor crystalline surface having a plane azimuth (110) or (023), or of a plane azimuth close thereto (plane azimuth substantially in parallel with the above-mentioned planes), in order to increase the speed of operation.


3
Shuji Ikeda, Satoshi Meguro, Soichiro Hashiba, Isamu Kuramoto, Atsuyoshi Koike, Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Nobuyuki Moriwaki: SRAM with dual word lines overlapping drive transistor gates. Antonelli Terry Stout & Kraus, August 24, 1993: US05239196 (57 worldwide citation)

A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.


4
Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato: Semiconductor integrated circuit device. Hitachi, Antonelli Terry Stout & Kraus, March 16, 1993: US05194749 (43 worldwide citation)

In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain prov ...


5
Toshiaki Yamanaka, Norio Suzuki, Yoshio Sakai, Yoshifumi Kawamoto, Osamu Minato, Koichiro Ishibashi, Nobuyuki Moriwaki, Satoshi Meguro: Static random-access memory having multilevel conductive layer. Hitachi, Antonelli Terry & Wands, August 1, 1989: US04853894 (43 worldwide citation)

A semiconductor memory having static cells each composed of two driver MOS transistors formed on a semiconductor substrate and two transfer MOS transistors and two load resistors, which are formed on the substrate and are connected to the drains of the driver MOS transistors, respectively. A conduct ...


6
Kazuhiro Komori, Satoshi Meguro, Toshiaki Nishimoto, Hitoshi Kume, Hideaki Yamamoto: Method of making tunnel EEPROM. Hitachi, Antonelli Terry Stout & Kraus, October 6, 1992: US05153144 (38 worldwide citation)

An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.


7
Toshiaki Yamanaka, Yoshio Sakai, Takashi Hashimoto, Takashi Nishida, Satoshi Meguro, Shuji Ikeda, Eiji Takeda: Semiconductor memory devices having stacked polycrystalline silicon transistors. Hitachi, Antonelli Terry Stout & Kraus, July 23, 1991: US05034797 (38 worldwide citation)

A semiconductor device having a CMIS structure for forming a static random access memory is disclosed which device can increase the packing density of the memory and reduce the stand-by power thereof. In this semiconductor device, a first MISFET of a first conductivity type is formed on and a substr ...


8
Satoshi Meguro, Kiyofumi Uchibori, Norio Suzuki, Makoto Motoyoshi, Atsuyoshi Koike, Toshiaki Yamanaka, Yoshio Sakai, Toru Kaga, Naotaka Hashimoto, Takashi Hashimoto, Shigeru Honjou, Osamu Minato: Semiconductor integrated circuit device. Hitachi, Antonelli Terry Stout & Kraus, January 9, 1996: US05483083 (37 worldwide citation)

A memory cell of the type employing a pair of cross-coupled CMOS inverters of a SRAM is provided in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETs. Each load MISFET of a memory cell consists of a source, drain and channel region formed of a semiconduc ...


9
Shuji Ikeda, Satoshi Meguro, Kotaro Nishimura, Sho Yamamoto, Nobuyoshi Tanimura: Method for making static random-access memory device. Hitachi, Antonelli Terry & Wands, September 27, 1988: US04774203 (37 worldwide citation)

A method of making a static random-access memory device or SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into at least a part of the polysilicon film for the purpose of increasing the threshold vo ...


10
Kazuhiro Komori, Takaaki Hagiwara, Satoshi Meguro, Toshiaki Nishimoto, Takeshi Wada, Kiyofumi Uchibori, Tadashi Muto, Hitoshi Kume, Hideaki Yamamoto, Tetsuo Adachi, Toshihisa Tsukada, Toshiko Koizumi: Semiconductor memory device. Hitachi, Antonelli Terry Stout & Kraus, November 20, 1990: US04972371 (35 worldwide citation)

An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor ...