1
Sargent S Eaton Jr, David R Wooten: Redundancy scheme for a dynamic RAM. Inmos Corporation, Edward D Manzo, June 21, 1983: US04389715 (84 worldwide citation)

A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective ...


2
Sargent S Eaton Jr, David R Wooten: High speed data transfer for a semiconductor memory. Inmos Corporation, Donald E Egan, James M Wetzel, August 10, 1982: US04344156 (65 worldwide citation)

A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality ...


3
John D Heightley, Sargent S Eaton Jr: Dummy cell arrangement for an MOS memory. December 7, 1982: US04363111 (30 worldwide citation)

A dummy cell arrangement is described for sensing the logic state of an accessed memory cell in an MOS memory in which a memory cell capacitor of a given size is associated with each memory cell. In the preferred embodiment, a plurality of dummy cells are included, each of which has a dummy capacito ...


4
Sargent S Eaton Jr: Method and apparatus of reducing latch-up susceptibility in CMOS integrated circuits. Inmos Corporation, Edward D Manzo, Roger R Wise, February 18, 1986: US04571505 (24 worldwide citation)

Method and apparatus for controlling latch-up in a CMOS circuit senses a power supply transition, clamps the substrate to ground in response to sensing a power supply transition, and releases the clamp after the power supply transition. A charge pump pumps the substrate illustratively to -3 volts. T ...


5
Sargent S Eaton Jr, David R Wooten: Folded bit line-shared sense amplifiers. Inmos Corporation, Cook Wetzel & Egan, September 21, 1982: US04351034 (21 worldwide citation)

A folded bit line-shared sense amplifier arrangement is described for sensing the logic state of an accessed memory cell in a dynamic MOS random access memory. In the preferred embodiment, a shared sense amplifier is positioned between and coupled to first and second bit lines via first and second i ...


6
Sargent S Eaton Jr, David R Wooten: MOS Capacitive bootstrapping trigger circuit for a clock generator. Inmos Corporation, Cook Wetzel & Egan, February 14, 1984: US04431927 (14 worldwide citation)

A trigger circuit is described for use in an MOS clock generator. The clock generator is the type which uses a conventional double bootstrapping circuit coupled to a control transistor to develop a high level clock output signal. The trigger circuit preconditions the control transistor to facilitate ...


7
Sargent S Eaton Jr: Voltage boosting circuits. RCA Corporation, H Christoffersen, A L Limberg, April 10, 1979: US04149232 (11 worldwide citation)

Voltage boosting circuits of a type using a plurality of inverters with parallelled inputs, each inverter arranged to pump charge into a respective pair of booster capacitors--rather than one respective booster capacitor--to develop an output voltage in each stage which is doubled in amplitude over ...


8
Sargent S Eaton Jr, Robert J Proebsting: Dynamic random access memory cell with increased signal margin. Mostek Corporation, January 1, 1985: US04491936 (11 worldwide citation)

A dynamic random access memory cell (30) includes an access transistor (32) having the gate terminal thereof connected to a word line (34) and the source and drain terminals thereof connected between a bit line (36) and a node (37). A charge storage capacitor (38) is connected between the node (37) ...


9
Sargent S Eaton Jr: High voltage clock generator. Mostek Corporation, October 12, 1982: US04354123 (7 worldwide citation)

A high voltage clock generator including an isolation and precharge circuit to charge a bootstrap capacitance at a time prior to driving the load capacitance to a higher voltage level. The first clock generator charges a load capacitance to the initial voltage level while the isolation precharge cir ...


10
Sargent S Eaton Jr: AND-gate clock. Mostek Corporation, September 15, 1981: US04289973 (5 worldwide citation)

An AND-gate clock having an input stage, an output stage, and an isolation stage. The input stage receives two signals, and gates them to produce a high signal. The output stage is used to drive a load typically having a large load capacitance when both signals are true. The isolation stage isolates ...