1
Charles Thomas Black, Joachim Norbert Burghartz, Sandip Tiwari, Jeffrey John Welser: Method for making three dimensional circuit integration. International Business Machines Corporation, Manny W Schecter, Scully Scott Murphy & Presser, December 7, 1999: US05998292 (410 worldwide citation)

The present invention relates to a method for interconnecting, through high-density micro-post wiring, multiple semiconductor wafers with lengths of about a millimeter or below. Specifically, the method of the present invention comprises etching at least one hole, defined by walls, at least partly t ...


2
Wei Chen, Theoren Perlee Smith III, Sandip Tiwari: Nano-structure memory device. International Business Machines Corporation, Robert M Trepp, February 3, 1998: US05714766 (184 worldwide citation)

A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocr ...


3
Bijan Davari, Devendra Kumar Sadana, Ghavam G Shahidi, Sandip Tiwari: Patterned SOI regions in semiconductor chips. International Business Machines Corporation, Robert M Trepp, December 25, 2001: US06333532 (160 worldwide citation)

A method and structure for forming patterned SOI regions and bulk regions is described wherein a silicon containing layer over an insulator may have a plurality of selected thickness' and wherein bulk regions may be suitable to form DRAM's and SOI regions may be suitable to form merged log ...


4
Sandip Tiwari: Low temperature semiconductor layering and three-dimensional electronic circuits using the layering. Cornell Research Foundation, Christopher E Blank, Jaeckle Fleischmann & Mugel, July 29, 2003: US06600173 (158 worldwide citation)

In a method for forming a three dimensional interconnected structure, sets of devices on receiver and donor semiconductor substrates. The donor substrate is implanted with two or more exfoliating implants, the substrates are bonded together to form a bonded structure that is heated until a portion o ...


5
Kevin Kok Chan, Christopher Peter D Emic, Erin Catherine Jones, Paul Michael Solomon, Sandip Tiwari: Method for making bonded metal back-plane substrates. International Business Machines Corporation, McGinn & Gibb P C, May 2, 2000: US06057212 (138 worldwide citation)

A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafer ...


6
Gregory T Baxter, Sandip Tiwari: Electronic gain cell based charge sensor. Cornell Research Foundation, Schwegman Lundberg Woessner & Kluth P A, October 11, 2005: US06953958 (121 worldwide citation)

A gated metal oxide semiconductor field effect transistor (MOSFET) gain cell is formed with a flow channel for molecule flow. The flow channel is formed under the gate, and between a source and drain of the transistor. The molecule flow modulates a gain of the transistor. Current flowing between the ...


7
Wei Chen, Theoren Perlee Smith III, Sandip Tiwari: Nano-structure memory device. International Business Machines Corporation, Robert M Trepp, August 10, 1999: US05937295 (83 worldwide citation)

A memory device and memory incorporating a plurality of the memory devices is described wherein each memory device has spaced apart source and drain regions, a channel, a barrier insulating layer, a nanocrystal or a plurality of nanocrystals, a control barrier layer, and a gate electrode. The nanocr ...


8
Allan M Hartstein, Michael A Tischler, Sandip Tiwari: Low voltage memory. International Business Machines Corporation, Blaney Harper, Ronald L Drumheller, April 16, 1996: US05508543 (80 worldwide citation)

A floating gate is inserted into the gate stack of an EEPROM cell. For an N channel EEPROM device, the floating gate is composed of a material having a conduction band edge (or fermi energy in the case of a metal or composite that includes a metal) at least one and preferably several kT electron vol ...


9
Steven John Holmes, Howard Leo Kalter, Sandip Tiwari, Jeffrey John Welser: Method of forming self-isolated and self-aligned 4F-square vertical FET-trench DRAM cells. November 13, 2001: US06316309 (79 worldwide citation)

A densely packed array of vertical semiconductor devices, having pillars, deep trench capacitors, vertical transistors, and methods of making thereof are disclosed. The pillars act as transistor channels, and may be formed utilizing the application of hybrid resist over a block of semiconductor mate ...


10
Sandip Tiwari, Samuel Jonas Wind: Method of making self-aligned dual gate MOSFET with an ultranarrow channel. Scully Scott Murphy & Presser, April 14, 1998: US05739057 (73 worldwide citation)

A dual gate field effect transistor with an ultra thin channel of substantially uniform width formed by a self-aligned process utilizing selective etching or controlled oxidation between different materials to form a vertical channel extending between source and drain regions, having a thickness in ...