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Boudreau Daniel A, Salas Edward R, Sandini James M: Distributed priority logic network.. Honeywell Inf Systems, August 1, 1984: EP0114523-A2 (3 worldwide citation)

A bus for coupling a plurality of units in a data processing system for the transfer of information therebetween. The units are coupled in a priority arrangement which is distributed, thereby providing priority logic in each of the units and allowing bus transfer cycles to be generated in an asynchr ...


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Johnson Robert B, Nibby Chester M Jr, Salas Edward R: Memoire a reconfiguration automatique, Memory system with automatic memory reconfiguration. Honeywell Information Systems, SMART & BIGGAR, April 9, 1985: CA1185376

ABSTRACT OF THE DISCLOSURE A memory system includes a plurality of memorycontrollers which connect to a common bus. Each memorycontroller includes reconfiguration apparatus whichenables the controller when faulty to be switched off lineand another controller to be substituted in its place soas to ma ...


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Boudreau Daniel A, Salas Edward R, Sandini James M: Logique de reseau a priorite repartie permettant a une unite a faible priorite de resider a une position a priorite elevee, Distributed priority network logic for allowing a low priority unit to reside in a high priority position. Honeywell Information Systems, SMART & BIGGAR, June 3, 1986: CA1205567

ABSTRACT A bus for coupling a plurality of units in a dataprocessing system for the transfer of informationtherebetween. The units are coupled in a priorityarrangement which is distributed thereby providingpriority logic in each of the units and allowing bustransfer cycles to be generated in an asyn ...


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Boudreau Daniel A, Salas Edward R, Sandini James M: Methode de verrouillage pour systeme a unite partagee et appareil realisant cette methode, Shared resource lockout operation method and apparatus. Honeywell Information Systems, SMART & BIGGAR, September 23, 1986: CA1211854

ABSTRACT OF THE DISCLOSURE A system having a plurality of units includes ashareable unit which is shareable between two or moreof the other units. Lock apparatus is provided inthe shareable unit to allow a first unit to lock theshareable unit so that no other unit attempting tolock the shareable uni ...


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Salas Edward R, Nibby Chester M Jr, Johnson Robert B: Appareil dadressage aligne par mots sequentiels, Sequential word aligned addressing apparatus. Honeywell Information Systems, SMART & BIGGAR, March 12, 1985: CA1183963

ABSTRACT OF THE DISCLOSURE A memory subsystem which couples to a multiword busfor processing memory requests received therefrom includesat least a pair of independently addressable dynamicmemory module units. Each memory unit includes a numberof rows of random access memory (RAM) chips. thesubsystem ...


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Salas Edward R, Fisher Edwin P, Johnson Robert B, Nibby Chester M Jr, Boudreau Daniel A: Dispositif et methode didentification pour memoire, Memory identification apparatus and method. Honeywell Information Systems, SMART & BIGGAR, August 12, 1986: CA1209714

ABSTRACT OF THE DISCLOSURE A memory system includes at least one or more memorymodule boards identical in construction and a singlecomputer board containing the control circuits forcontrolling memory operations. Each board plugs into themain board and includes a memory section having a numberof rows ...