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Xavier Baie
Doris Bruce B, Chidambarrao Dureseti, Baie Xavier, Mandelman Jack A, Sadana Devendra K, Schepis Dominic J: (fet) Having stress channel and its manufacturing method. Internatl Business Mach Corp &Lt IBM&Gt, July 8, 2004: JP2004-193596 (2 worldwide citation)

PROBLEM TO BE SOLVED: To provide a field-effect transistor whose charge carrier mobility increases by the stress of an electric current channel 22.SOLUTION: The direction of the stress is that in which a current flows (vertical direction). For a PFET device, the stress is compressive stress, while t ...


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Xavier Baie
Doris Bruce B, Chidambarrao Dureseti, Baie Xavier, Mandelman Jack A, Sadana Devendra K: Field effect transistor with stressed channel and method for making same. International Business Machines Corporation, December 21, 2005: TWI246180

Field effect transistor with increased charge carrier mobility due to stress in the current channel 22. The stress is in the direction of current flow (longitudinal). In PFET devices, the stress is compressive; in NFET devices, the stress is tensile. The stress is created by a compressive film 34 in ...


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Leobandung Effendi, Sadana Devendra K, Schepis Dominic J, Shahidi Ghavam: Silicon-on-insulator structure and manufacture thereof. Internatl Business Mach Corp &Lt IBM&Gt, September 8, 2000: JP2000-243944 (13 worldwide citation)

PROBLEM TO BE SOLVED: To provide a planar silicon-on-insulator(SOI) structure and a method for manufacturing the structure. SOLUTION: The SOI structure has a silicon wafer 10, an oxide layer 12 and a silicon layer 14. A trench is formed as extended from an upper surface of the structure to the silic ...


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Desouza Joel P, Greiner James H, Sadana Devendra K: Controlled silicon doping of iii-v compounds by thermal oxidation of silicon capping layer.. Ibm, September 4, 1991: EP0444465-A2 (2 worldwide citation)

The method for silicon doping of III-V compounds by depositing a layer of silicon (12) on the surface of a III-V compound substrate (10) and subjecting the silicon capped substrate (10) to thermal oxidation at temperatures and in an oxidizing atmosphere sufficient to cause silicon to diffuse into th ...


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Sadana Devendra K, Bedell Stephen W, Chen Tze Chiang, Choe Kwang Su, Fogel Keith E: Patterned strained (stress deformation) silicon for high-performance circuit. Internatl Business Mach Corp &Lt IBM&Gt, July 29, 2004: JP2004-214629 (2 worldwide citation)

PROBLEM TO BE SOLVED: To develop a new improved method for forming a relaxed SiGe-on-insulator substrate material which is thermodynamically stable with respect to the generation of a defect.SOLUTION: Silicon to which tensile stress is applied is formed by epitaxially growing over the whole SiGe all ...


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Kiewra Edward W, Koester Steven J, Sadana Devendra K, Shahidi Ghavam, Sun Yanning: Buried channel mosfet using iii-v compound semiconductors and high k gate dielectrics. International Business Machines Corporation, Kiewra Edward W, Koester Steven J, Sadana Devendra K, Shahidi Ghavam, Sun Yanning, GROLZ Edward W, December 27, 2007: WO/2007/149581 (2 worldwide citation)

A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barr ...


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Kevin K Chan, Doris Bruce B, Guarini Kathryn W, Leong Meikei, Narasimha Shreesh, Reznicek Alexander, Kern Lim, Sadana Devendra K, Shi Leathen, Sleight Jeffrey W, Yang Min: Strained silicon complementary metal oxide semiconductor on hybrid crystal orientation. Internatl Business Mach Corp &Lt IBM&Gt, November 4, 2005: JP2005-311367 (2 worldwide citation)

PROBLEM TO BE SOLVED: To provide an integrated semiconductor device formed on a substrate having different crystal orientation.SOLUTION: A method of forming a hybrid substrate containing strained Si and a strained Si containing hybrid substrate formed by this method are provided. In the present inve ...


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Fried David M, Nowak Edward J, Rainey Beth Ann, Sadana Devendra K: Fin fet devices from bulk semiconductor and method for forming. Ibm, May 25, 2005: EP1532659-A2 (1 worldwide citation)

The present invention thus provides a device structure and method for forming fin Field Effect Transistors (FETs) that overcomes many of the disadvantages of the prior art. Specifically, the device structure and method provides the ability to form finFET devices from bulk semiconductor wafers while ...


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Shahidi Ghavam G, Bedell Stephen W, Sadana Devendra K, Fogel Keith E: Method of forming substantially relaxed, high-quality sige-on-insulator substrate material, substrate material, and hetero structure. Internatl Business Mach Corp &Lt IBM&Gt, December 24, 2004: JP2004-363592 (1 worldwide citation)

PROBLEM TO BE SOLVED: To provide a method of forming a substantially relaxed high-quality SiGe-on-insulator substrate material using SIMOX and Ge interdiffusion.SOLUTION: In order to form an injection rich area in a Si-containing substrate, ions are injected into Si-containing substrate at the begin ...



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