1
Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii: Resistance variable memory apparatus. Panasonic Corporation, McDermott Will & Emery, August 2, 2011: US07990754 (42 worldwide citation)

A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated w ...


2
Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii, Yoshihiko Kanzawa: Resistance change nonvolatile memory device. Panasonic Corporation, McDermott Will & Emery, April 5, 2011: US07920408 (37 worldwide citation)

Memory cells (MC) are formed at intersections of bit lines (BL) extending in the X direction and word lines (WL) extending in the Y direction. A plurality of basic array planes sharing the word lines (WL), each formed for a group of bit lines (BL) aligned in the Z direction, are arranged side by sid ...


3
Ryotaro Azuma, Kazuhiko Shimakawa, Satoru Fujii: Resistance variable memory apparatus. Panasonic Corporation, McDermott Will & Emery, April 10, 2012: US08154909 (26 worldwide citation)

A resistance variable memory apparatus (100) of the present invention includes a current suppressing element (116) which is connected in series with each resistance variable layer (114) and whose threshold voltage is VF, and is configured to apply a first voltage V1 to a first wire (WL) associated w ...


4
Ken Kawai, Kazuhiko Shimakawa, Shunsaku Muraoka, Ryotaro Azuma: Forming method for variable resistance nonvolatile memory element, and variable resistance nonvolatile memory device. Panasonic Corporation, Wenderoth Lind & Ponack, March 12, 2013: US08395925 (13 worldwide citation)

An optimum forming method of performing a forming for a variable resistance element to maximize an operation window of the variable resistance element is provided. The forming method is used to initialize a variable resistance element (100). The forming method includes: a determination step (S35) of ...


5
Takeshi Takagi, Shunsaku Muraoka, Ryotaro Azuma, Kunitoshi Aono: Nonvolatile storage device and method for writing into the same. Panasonic Corporation, Wenderoth Lind & Ponack, February 28, 2012: US08125817 (10 worldwide citation)

To provide a nonvolatile storage device (100) which is capable of achieving stable operation and includes variable resistance elements. The nonvolatile storage device (100) includes: memory cells (M111, M112, . . .) each of which is provided at three-dimensional cross-points between word lines (WL0, ...


6
Ryotaro Azuma, Kazuhiko Shimakawa, Shunsaku Muraoka, Ken Kawai: Nonvolatile variable resistance memory element writing method, and nonvolatile variable resistance memory device. Panasonic Corporation, Wenderoth Lind & Ponack, November 6, 2012: US08305795 (9 worldwide citation)

To provide a variable resistance element writing method that, even when a variable resistance element has a possibility of becoming a half LR state, can ensure a maximum resistance change window by correcting the variable resistance element to a normal low resistance state. In a method of writing da ...


7
Ryotaro Azuma, Makoto Kojima: Booster circuit. Panasonic Corporation, McDermott Will & Emery, July 28, 2009: US07567118 (9 worldwide citation)

An oscillation circuit 10 outputs oscillation clocks 100 different in phase, and a four-phase clock generation circuit 20 generates a four-phase clock 200 based on a difference in phase between the oscillation clocks 100. A four-phase clock transfer control circuit 50 controls whether to transfer th ...


8
Yuuichirou Ikeda, Kazuhiko Shimakawa, Yoshihiko Kanzawa, Shunsaku Muraoka, Ryotaro Azuma: Variable resistance nonvolatile memory device. Panasonic Corporation, Wenderoth Lind & Ponack L, May 14, 2013: US08441837 (7 worldwide citation)

A nonvolatile resistance variable memory device (100) includes memory cells (M11, M12, . . . ) in each of which a variable resistance element (R11, R12, . . . ) including a variable resistance layer placed between and in contact with a first electrode and a second electrode, and a current steering e ...


9
Yuichiro Ikeda, Kazuhiko Shimakawa, Ryotaro Azuma: Variable resistance nonvolatile memory device. Panasonic Corporation, Wenderoth Lind & Ponack L, June 18, 2013: US08467229 (7 worldwide citation)

In a nonvolatile memory device, basic array planes (0 to 3) have respective first via groups (121 to 124) that interconnect only even-layer bit lines in the basic array planes, and respective second via groups (131 to 134) that interconnect only odd-layer bit lines in the basic array planes, the fir ...


10
Ryotaro Azuma, Kazuhiko Shimakawa: Cross point variable resistance nonvolatile memory device. Panasonic Corporation, Wenderoth Lind & Ponack L, May 14, 2013: US08441839 (7 worldwide citation)

A cross point variable resistance nonvolatile memory device includes memory cells having the same orientation for stable characteristics of all layers. Each memory cell (51) is placed at a different one of cross points of bit lines (53) in an X direction and word lines (52) in a Y direction formed i ...