1
David A Courtright, Ryan C Kinter: Scratchpad RAM memory accessible in parallel to a primary cache. Mips Technologies, Cooley Godward, August 6, 2002: US06430655 (28 worldwide citation)

A low-latency scratchpad RAM memory system is disclosed. The scratchpad RAM memory system can be accessed in parallel to a primary cache. Parallel access to the scratchpad RAM memory can be designed to be independent of a corresponding cache tag RAM, thereby enabling the scratchpad RAM memory to be ...


2
Ryan C Kinter, Scott M McCoy, Gideon D Intrater: Apparatus and method for discovering a scratch pad memory configuration. MIPS Technologies, Cooley Godward, December 28, 2004: US06836833 (21 worldwide citation)

The invention includes a method of debugging an embedded processor. Scratch pad memory of an embedded processor is accessed to form a configuration file characterizing the configurations of scratch pad regions of the scratch pad memory. The embedded processor is debugged using information from the c ...


3
Darren M Jones, Ryan C Kinter, Thomas A Petersen, Sanjay Vishin: Leaky-bucket thread scheduler in a multithreading microprocessor. MIPS Technologies, Sterne Kessler Goldstein & Fox PLLC, July 6, 2010: US07752627 (20 worldwide citation)

A leaky-bucket style thread scheduler for scheduling concurrent execution of multiple threads in a microprocessor is provided. The execution pipeline notifies the scheduler when it has completed instructions. The scheduler maintains a virtual water level for each thread and decreases it each time th ...


4
Darren M Jones, Ryan C Kinter, G Michael Uhler, Sanjay Vishin: Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions. MIPS Technologies, Sterne Kessler Goldstein & Fox P L L C, December 14, 2010: US07853777 (12 worldwide citation)

An apparatus for reducing instruction re-fetching in a multithreading processor configured to concurrently execute a plurality of threads is disclosed. The apparatus includes a buffer for each thread that stores fetched instructions of the thread, having an indicator for indicating which of the fetc ...


5
Sanjay Vishin, Kevin D Kissell, Darren M Jones, Ryan C Kinter: Smart memory based synchronization controller for a multi-threaded multiprocessor SoC. MIPS Technologies, Sterne Kessler Goldstein & Fox PLLC, September 22, 2009: US07594089 (11 worldwide citation)

A memory interface for use with a multiprocess memory system having a gating memory, the gating memory associating one or more memory access methods with each of a plurality of memory locations of the memory system wherein the gating memory returns a particular one access method for a particular one ...


6
Michael Gottlieb Jensen, Darren M Jones, Ryan C Kinter, Sanjay Vishin: Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages. MIPS Technologies, Sterne Kessler Goldstein & Fox P L L C, February 16, 2010: US07664936 (11 worldwide citation)

An apparatus for scheduling dispatch of instructions among a plurality of threads being concurrently executed in a multithreading processor is provided. The apparatus includes an instruction decoder that generate register usage information for an instruction from each of the threads, a priority gene ...


7
Michael Gottlieb Jensen, Ryan C Kinter: Multithreading instruction scheduler employing thread group priorities. MIPS Technologies, Sterne Kessler Goldstein & Fox P L L C, February 9, 2010: US07660969 (9 worldwide citation)

A concurrent instruction dispatch apparatus includes a group indicator for each of a plurality of threads that indicates which one of a plurality of groups of the threads the thread belongs to. A group priority indicator for each group indicates an instruction dispatch priority relative to the other ...


8
Darren M Jones, Ryan C Kinter, Kevin D Kissell, Thomas A Petersen: Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler. MIPS Technologies, Sterne Kessler Goldstein & Fox P L L C, November 3, 2009: US07613904 (8 worldwide citation)

A bifurcated instruction scheduler for dispatching instructions of multiple threads concurrently executing in a multithreading processor is provided. The scheduler includes a first portion within a reusable core that is not customizable by a customer, a second portion outside the core that is custom ...


9
Soumya Banerjee, Michael Gottlieb Jensen, Ryan C Kinter: Three-tiered translation lookaside buffer hierarchy in a multithreading microprocessor. MIPS Technologies, Sterne Kessler Goldstein & Fox PLLC, July 7, 2009: US07558939 (8 worldwide citation)

A three-tiered TLB architecture in a multithreading processor that concurrently executes multiple instruction threads is provided. A macro-TLB caches address translation information for memory pages for all the threads. A micro-TLB caches the translation information for a subset of the memory pages ...


10
Michael Gottlieb Jensen, Darren M Jones, Ryan C Kinter, Sanjay Vishin: Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency. MIPS Technologies, Sterne Kessler Goldstein & Fox P L L C, February 2, 2010: US07657891 (7 worldwide citation)

A multithreading processor for concurrently executing multiple threads is provided. The processor includes an execution pipeline and a thread scheduler that dispatches instructions of the threads to the execution pipeline. The execution pipeline detects a stalling event caused by a dispatched instru ...