1
Lubin Gee, Pearl Cheng, Yogendra Bobra, Rustam Mehta: Intelligent electrically programmable and electrically erasable ROM. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 17, 1984: US04460982 (160 worldwide citation)

An E.sup.2 PROM is disclosed which provides automatic programming verification. Before data is written into the cells, the cells are automatically erased. The contents of the cells are checked to verify that erasing has been completed. If it has not, erasing is continued until the cells are erased. ...


2
Hyung Kyu Lim, Jae Yeong Do, Rustam Mehta: Redundancy circuit for use in a semiconductor memory device. SamSung Semiconductor & Telecommunication, Robert E Bushnell, December 27, 1988: US04794568 (20 worldwide citation)

A normal decoder and a redundant decoder having address program devices are used for the replacement of bad cells. The number of address program devices is one more than the number of input address bits for selecting a normal row or column. The input signals of the additional program device are comp ...


3
Tushar Gheewala, Rustam Mehta, Prab Varma: Storage element for delay testing. CrossCheck Technology, Townsend and Townsend and Crew, November 28, 1995: US05471152 (19 worldwide citation)

A storage element for testing delay paths in integrated circuits is described. The storage element may be used in integrated circuits having matrices of probe and sense lines. The storage element generates a logic transition on an input to a delay path, the logic transition being closely synchronize ...


4
Rustam Mehta, Stephen F Dreyer: Dynamic MOS RAM. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 26, 1977: US04038646 (18 worldwide citation)

An improved dynamic MOS RAM employing capacitive storage memory cells having a single active device per cell. The RAM includes several improved circuits and techniques which reduce power consumption and pattern sensitivity and which also provide a higher speed memory. Complementary input/output line ...


5
Tushar Gheewala, Rustam Mehta, Timothy Saxe: Method and structure for routing power for optimum cell utilization with two and three level metal in a partially predesigned integrated circuit. CrossCheck Technology, Townsend and Townsend Khourie and Crew, July 25, 1995: US05436801 (1 worldwide citation)

An integrated circuit structure which employs at least two metal levels overlying an array of circuit elements. Each metal level contains signal routing resources which can be used for supplying power and interconnecting circuit elements. The metal levels include a first metal level directly overlyi ...