1
William B Ledbetter Jr, Russell A Reininger: Method for data bus snooping in a data processing system by selective concurrent read and invalidate cache operation. Motorola, Robert L King, June 2, 1992: US05119485 (166 worldwide citation)

A bus snoop control method for maintaining coherency between a write-back cache and main memory during memory accesses by an alternate bus master. The method and apparatus incorporates an option to source `dirty` or altered data from the write-back cache to the alternate bus master during a memory r ...


2
Robin W Edenfield, William B Ledbetter Jr, Russell A Reininger: System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address. Motorola, Charlotte B Whitaker, October 13, 1992: US05155824 (103 worldwide citation)

A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a ...


3
Russell A Reininger, William B Ledbetter Jr, Robin W Edenfield, Van B Shahan, Ralph C McGarity, Eric E Quintana: Memory access serialization as an MMU page attribute. Motorola, Charlotte B Johnson Whitaker, December 24, 1991: US05075846 (37 worldwide citation)

A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independentl ...


4
Craig C Hunter, Russell A Reininger: Clock scan design from sizzle global clock and method therefor. Motorola, May 5, 1998: US05748645 (18 worldwide citation)

A scan based test methodology generates conventional functional clocks (CLK1 and CLK2) and test clocks (CLKA and CLKB) from a single input clock (GCLK). The methodology allows an integrated circuit (10) designed according to it to be tested at the part's operating frequency. Also, the test methodolo ...


5
Bryan Black, Marvin A Denman, Lee E Eisen, Robert T Golla, Albert J Loper Jr, Soummya Mallick, Russell A Reininger: Method and system for recoding noneffective instructions within a data processing system. International Business Machines Corporation, Michael A Davis Jr, Andrew J Dillon, April 8, 1997: US05619408 (14 worldwide citation)

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved ...