1
Rajiv V Joshi, Rouwaida Kanj: In-situ design method and system for improved memory yield. International Business Machines Corporation, Tutunjian & Bitetto P C, Preston J Young Esq, May 1, 2012: US08170857 (85 worldwide citation)

A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin informat ...


2
Rajiv V Joshi, Rouwaida Kanj, Jayakumaran Sivagnaname: Half-select compliant memory cell precharge circuit. International Business Machines Corporation, Tutunjian & Bitetto P C, Brian Verminski Esq, July 6, 2010: US07751267 (1 worldwide citation)

A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in acco ...


3
Timothy S Lehner, Khalid Rahmat, Ronald D Rose, Rouwaida Kanj: Circuit and method for modeling I/O. International Business Machines Corporation, Ibm Microelectronics, October 2, 2003: US20030188267-A1

A circuit model and method for modeling circuit waveforms. The elements present in the basic model are capacitors and ideal current sources. The adaptability and accuracy of the model is made possible by explicitly tabulating all element values as simultaneous functions of all input and output volta ...


4
Rajiv V Joshi, Rouwaida Kanj, Jayakumaran Sivagnaname: Half-select compliant memory cell precharge circuit. Keusey Tutunjian & Bitetto PC, January 29, 2009: US20090027983-A1

A programmable precharge circuit includes a plurality of transistors. Each transistor has a different threshold voltage from other transistors of the plurality of transistors. Each transistor is configured to connect a supply voltage to a node, and the node is selectively coupled to bitlines in acco ...


5
Rajiv V Joshi, Rouwaida Kanj, Keunwoo Kim: System and method for optimization and predication of variability and yield in integrated ciruits. Keusey Tutunjian & Bitetto PC, March 12, 2009: US20090070716-A1

A system and method for designing a circuit includes generating physics based equations to describe phenomena of a circuit component, representing physical device geometry by correlating the physical device geometry with features of a circuit component design, and integrating the physical based equa ...


6
Ching Te K Chuang, Fook Luen Heng, Rouwaida Kanj, Keunwoo Kim, Jin Fuw Lee, Saibal Mukhopadhyay, Sani Richard Nassif, Rama Nand Singh: Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields. International Business Machines Corporation, July 14, 2011: US20110173577-A1

Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated cir ...


7
Rajiv V Joshi, Rouwaida Kanj: IN-SITU DESIGN METHOD AND SYSTEM FOR IMPROVED MEMORY YIELD. TUTUNJIAN & BITETTO P C, May 27, 2010: US20100131259-A1

A system and method for designing integrated circuits includes determining a target memory module for evaluation and improvement by evaluating performance variables of the memory module. The performance variables are statistically simulated over subset combinations of variables based on pin informat ...



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