1
Charles M Corbalis, Ross S Heitkamp, Mike M Wu, Amar Gupta: Flexible destination address mapping mechanism in a cell switching communication controller. Stratacom, Blakely Sokoloff Taylor & Zafman, July 4, 1995: US05430715 (137 worldwide citation)

A mechanism for routing a communication cell in a cell switching communication controller that employs multiple path identifier masking functions selected by a header control field in the communication cell and that employs a content addressable memory comprising a plurality of entries, wherein each ...


2
Charles M Corbalis, Ross S Heitkamp, Rafael Gomez: Bandwidth and congestion control for queue channels in a cell switching communication controller. Stratacom, Blakely Sokoloff Taylor & Zafman, October 25, 1994: US05359592 (114 worldwide citation)

A mechanism for buffering communication cells in a communication controller, wherein a cell queuing circuit provides a cell loss priority mechanism, and wherein the cell queuing circuit determines service states for queue channels according to bandwidth allocation parameters. The service states incl ...


3
Ross S Heitkamp, Charles M Corbalis, William N Bedell, Frederick R Enns, Amar S Gupta, John D Weisbloom: Broadband switching fabric in a communication controller. Stratacom, Blakely Sokoloff Taylor & Zafman, June 6, 1995: US05422880 (75 worldwide citation)

A method and apparatus for exchanging communication cells in a communication controller, wherein an arbiter determines transmission requests for each of a plurality of communication modules in the communication controller. Each communication module has a transmit signal line and a receive signal lin ...


4
Ross S Heitkamp, Chang Hong Wu: Clock controller for controlling the switching to redundant clock signal without producing glitches by delaying the redundant clock signal to match a phase of primary clock signal. Juniper Networks, Harrity & Snyder, January 6, 2004: US06675307 (10 worldwide citation)

A system and method for controlling clocking signals including a clock controller that includes a first input operable to receive a first clock signal having a first frequency, a second input operable to receive a second clock having a same frequency as the first clock signal but of arbitrary phase, ...