1
John Lockwood, Ronald Loui, James Moscola, Michael L Pachos: Methods, systems, and devices using reprogrammable hardware for high-speed processing of streaming data to find a redefinable pattern and respond thereto. Washington University, Sonnenschein Nath & Rosenthal, August 15, 2006: US07093023 (125 worldwide citation)

A reprogrammable packet processing system for processing a stream of data is disclosed herein. A reprogrammable data processor is implemented with a programmable logic device (PLD), such as a field programmable gate array (FPGA), that is programmed to determine whether a stream of data applied there ...


2
John Lockwood, Ronald Loui, James Moscola, Michael Pachos: Methods, systems, and devices using reprogrammable hardware for high-speed processing of streaming data to find a redefinable pattern and respond thereto. Thompson Coburn, November 27, 2003: US20030221013-A1

A reprogrammable packet processing system for processing a stream of data is disclosed herein. A reprogrammable data processor is implemented with a programmable logic device (PLD), such as a field programmable gate array (FPGA), that is programmed to determine whether a stream of data applied there ...