1
Scott Dion Rodgers, Rohit Vidwans, Joel Huang, Michael A Fetterman, Kamla Huck: Method and apparatus for generating event handler vectors based on both operating mode and event type. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 30, 1999: US05889982 (77 worldwide citation)

A method and apparatus for handling events, such as those which occur in a processor. An event vector is formed by combining event type information indicating a type of event in the processor and mode information indicating an operating mode of the processor. A microcode event handler vector is gene ...


2
Rohit Vidwans, James A Beavens: Method and system for efficient cache memory updating with a least recently used (LRU) protocol. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 4, 2003: US06643742 (12 worldwide citation)

A method of and system for concurrently processing multiple memory requests. The first and second memory requests contain a linear address. A search for the cache entry in a cache block is issued in response to the linear address. After locating the cache entries associated with the memory requests, ...


3
Jeffrey M Abramson, Haitham Akkary, Andrew F Glew, Glenn J Hinton, Kris G Konigsfeld, Rohit Vidwans: Method and apparatus for handling code segment violations in a computer system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 13, 1998: US05708843 (11 worldwide citation)

A memory operation is issued in a processor. Upon detecting both that the memory operation produces a code segment violation and that the memory operation is blocked at retirement, a blocking signal is produced to block a bus access responsive to the memory operation. A second signal signifies that ...