1
Roger P Gregor: Bidirectional level shifting interface circuit. International Business Machines, Arthur J Samodovitz, January 28, 1992: US05084637 (40 worldwide citation)

A bidirectional level shifting interface circuit has first and second I/O ports and an FET with a drain-source channel connected between the first and second I/O ports. The first I/O port is connected to an I/O port of a first digital circuit operating at a relatively low supply voltage, and the sec ...


2
Janice M Adams, Keith M Carrig, Roger P Gregor, Daniel R Menard: Method and apparatus for routing low-skew clock networks. International Business Machines Corporation, Eugene I Shkurko Esq, McGinn & Gibb PLLC, March 20, 2001: US06204713 (28 worldwide citation)

An integrated circuit chip comprises a plurality of clock distribution sub-networks each including a clock input for receiving a clock signal, each of the clock distribution sub-networks having a capacitance, as seen from the clock input, substantially equivalent to others of the clock distribution ...


3
Terry C Coughlin Jr, Roger P Gregor, Steven F Oakland, Douglas W Stout: CMOS state saving latch. International Business Machines Corporation, Michael F Hoffman, Hoffman Warnick & D&apos Alessandro, December 10, 2002: US06493257 (26 worldwide citation)

A state saving circuit and method for using the same. The circuit comprises a first latch powered by an uninterrupted power supply, wherein the first latch includes a first pair of cross coupled inverters for storing data, and includes an input cut-off control for isolating the data in the first pai ...


4
Paul H Bergeron, Keith M Carrig, Alvar A Dean, Roger P Gregor, David J Hathaway, David E Lackey, Harold E Reindel, Larry Wissel: Latch clustering for power optimization. International Business Machines Corporation, Richard M Kotulak Esq, McGinn & Gibb PLLC, August 19, 2003: US06609228 (22 worldwide citation)

A method and structure of clock optimization including creating an initial placement of clock feeding circuits according to clock signal requirements; identifying clusters of the clock feeding circuits, wherein each cluster includes a distinct clock signal supply device to which each clock feeding c ...


5
Robert A Gottschall, Roger P Gregor, James P Libous: Dual-pitch perimeter flip-chip footprint for high integration asics. International Business Machines Corporation, John R Pivnichny, Whitham Curtis & Whitham, March 14, 2000: US06037677 (21 worldwide citation)

A connection array for a chip provides a substantial increase in numbers of signal connection locations and a power distribution arrangement of improved robustness and noise immunity while accommodating multiple power supply voltages by providing pairs of sub-arrays aligned with chip edges and signa ...


6
Roger P Gregor, Steven F Oakland, Toshiharu Saitoh, Sebastian T Ventrone: Low power LSSD flip flops and a flushable single clock splitter for flip flops. International Business Machines Corporation, Ronald A Kaschak, Schmeiser Olsen & Watts, October 16, 2001: US06304122 (17 worldwide citation)

This invention reduces power in flip flop apparatuses by providing flip flop apparatuses that have fewer clock trees than prior art flip flops yet still support some or all of the Level Sensitive Scan Design (LSSD) functionality. In preferred embodiments of the present invention, one clock tree is u ...


7
Roger P Gregor, James P Libous: Multiple power distribution for delta-I noise reduction. International Business Machines Corporation, John R Pivnichny, McGuireWoods, January 1, 2002: US06335494 (8 worldwide citation)

Power layers of a multi-layer connection structure forming a power distribution network are partitioned to accommodate all necessary voltages for one or more chips connected thereto in each power layer. By doing so, and rearranging vias as permitted by such partitioning via length is reduced while v ...


8
Roger P Gregor, Eugene J Nosowicz: Pulse generator with controlled output characteristics. International Business Machines Corporation, Arthur J Samodovitz, December 9, 2003: US06661121 (1 worldwide citation)

A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the out ...


9
Roger P Gregor, Eugene J Nosowicz: Pulse generator with controlled output characteristics. International Business Machines Corporation, Arthur J Samodovitz, IBM Corporation N50 040 4, March 20, 2003: US20030052546-A1

A pulse generation circuit delivers an output pulse whose width is tailored to the load. The pulse generation circuit comprises the following components. A drive circuit has an input coupled to receive a clock signal and an output coupled to drive a load. A comparator has an input coupled to the out ...