1
Andrew Crosland, Roger May, Edward Flaherty, Andrew Draper: Embedded processor with watchdog timer for programmable logic. Altera Corporation, Townsend and Townsend and Crew, March 4, 2008: US07340596 (73 worldwide citation)

A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) ...


2
Andrew Crosland, Roger May, Edward Flaherty, Andrew Draper: Embedded processor with watchdog timer for programmable logic. Altera Corporation, Townsend and Townsend and Crew, March 25, 2008: US07350178 (51 worldwide citation)

A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) ...


3
Roger May, James Tyson, Edward Flaherty, Mark Dickinson: Bus architecture for system on a chip. Altera Corporation, O&apos Keefe Egan & Peterman, June 1, 2004: US06745369 (44 worldwide citation)

A multiple bus architecture for a system on a chip including bridges for decoupling clock frequencies of individual bus masters from peripherals they are accessing. Each bridge interfaces to all bus masters in the system that require access to the peripherals it interfaces to.


4
Roger May, Andrew Draper: Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream. Altera Corporation, Townsend and Townsend and Crew, May 4, 2004: US06732263 (28 worldwide citation)

A method and apparatus for configuring a digital system having a programmable logic device and embedded logic from a configuration source that supplies a single serialized configuration bit stream for configuring both the programmable logic device and the embedded logic.


5
Roger May, Igor Kostarnov, Edward H Flaherty, Mark Dickinson: I/O circuitry shared between processor and programmable logic portions of an integrated circuit. Altera Corporation, Steven J Cahill, Townsend and Townsend and Crew, October 12, 2004: US06803785 (19 worldwide citation)

The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same ...


6
Roger May, Andrew Crosland, Edward Flaherty: Programmable logic device. Altera Corporation, Townsend and Townsend and Crew, April 11, 2006: US07026840 (14 worldwide citation)

A programmable logic device is provided with multiple power supplies such that, in one mode of operation, power can be disconnected from at least one part of the programmable logic device, while maintaining power at least to an interface component of the programmable logic device, or to a memory com ...


7
Roger May, Andrew Draper, Paul Metzgen, Neil Thorne: Embedded processor with dual-port SRAM for programmable logic. Altera Corporation, Townsend and Townsend and Crew, J Matthew Zigmant, August 22, 2006: US07096324 (10 worldwide citation)

Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or regist ...


8
Roger May, Andrew Draper, Paul Metzgen, Neil Thorne: Embedded processor with dual-port SRAM for programmable logic. Altera Corporation, Townsend and Townsend and Crew, J Matthew Zigmant, June 9, 2009: US07546424 (8 worldwide citation)

Methods and apparatus for programmable logic devices including embedded processors having a dual-port SRAMs. A programmable logic integrated circuit includes a programmable logic portion having a plurality of logic elements, programmably configurable to implement user-defined combinatorial or regist ...


9
Roger May, Igor Kostarnov, Edward H Flaherty, Mark Dickinson: I/O circuitry shared between processor and programmable logic portions of an integrated circuit. Altera Corporation, Fish & Neave IP Group of Ropes & Gray, December 27, 2005: US06980024 (5 worldwide citation)

The present invention provides circuitry and methods for sharing I/O pins between a programmable logic portion and an embedded processor portion of a chip. The circuits in the programmable logic portion and the embedded processor portion can access data signals from and send data signals to the same ...


10
Roger May, Andrew Draper: Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream. Altera Corporation, Townsend and Townsend and Crew, March 11, 2008: US07343483 (4 worldwide citation)

A method and apparatus for configuring a digital system having a programmable logic device and embedded logic from a configuration source that supplies a single serialized configuration bit stream for configuring both the programmable logic device and the embedded logic.