1
Roger E Tipley: Split transaction protocol for the peripheral component interconnect bus. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, July 2, 1996: US05533204 (122 worldwide citation)

A computer system including the peripheral component interconnect (PCI) bus, including the LOCK# and STOP# signals and also having an extra sideband signal for supporting posted read transactions. The extra sideband signal, referred to as POST#, is used in conjunction with the LOCK# and STOP# signal ...


2
Roger E Tipley, Philip C Kelly: Method and apparatus for incorporating cache line replacement and cache write policy information into tag directories in a cache system. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, June 28, 1994: US05325504 (90 worldwide citation)

A method and apparatus for incorporating cache line replacement and cache write policy information into the tag directories in a cache system. In a 2 way set-associative cache, one bit in each way's tag RAM is reserved for LRU information, and the bits are manipulated such that the Exclusive-OR of e ...


3
Roger E Tipley: Method and apparatus for achieving multilevel inclusion in multilevel cache hierarchies. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, November 29, 1994: US05369753 (85 worldwide citation)

A method for achieving multilevel inclusion in a computer system with first and second level caches. The caches align on a "way" basis by their respective cache controllers communicating with each other which blocks of data they are replacing and which of their cache ways are being filled with data. ...


4
John A Landry, Jeff W Wolford, Walter G Fry, Roger E Tipley: Method and apparatus for testing and debugging a tightly coupled mirrored processing system. Compaq Computer, Pravel Hewitt Kimball & Krieger, July 18, 1995: US05434997 (67 worldwide citation)

A method and apparatus for operating tightly coupled mirrored processors in a computer system. A plurality of CPU boards are coupled to a processor/memory bus, commonly called a host bus. Each CPU board includes a processor as well as various ports, timers, and interrupt controller logic local to th ...


5
Mike T Jackson, Jeffrey C Stevens, Roger E Tipley: Multiprocessor cache snoop access protocol wherein snoop means performs snooping operations after host bus cycle completion and delays subsequent host bus cycles until snooping operations are completed. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, August 2, 1994: US05335335 (54 worldwide citation)

A method and apparatus for enabling a dual ported cache system in a multiprocessor system to guarantee snoop access to all host bus cycles which require snooping. The cache controller includes a set of latches coupled to the host bus which it uses to latch the state of the host bus during a snoop cy ...


6
Jeffrey C Stevens, Mike T Jackson, Roger E Tipley, Jens K Ramsey, Sompong Olarig, Philip C Kelly: Multiprocessor cache abitration. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, June 20, 1995: US05426765 (53 worldwide citation)

A method for arbitrating between processor and host bus snoop accesses to a cache subsystem in a multiprocessor system where the processor does not allow for processor cycle aborts. When a processor access and a snoop access both occur and no tag access or tag modify cycle is currently being perform ...


7
Roger E Tipley, Michael Moriarty, Mark Taylor: Prioritization of microprocessors in multiprocessor computer systems. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, July 9, 1996: US05535395 (51 worldwide citation)

Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of ( ...


8
Michael J Collins, Roger E Tipley: True least recently used replacement method and apparatus. Compaq Computer, Pravel Hewitt Kimball & Krieger, June 28, 1994: US05325511 (41 worldwide citation)

An apparatus for performing Least Recently Used techniques for a four way set associative cache system which includes a random access memory (RAM) which stores the ways representing the least recently used (LRU), most recently used (MRU) and LRU+1. The MRU-1 is developed by XORing the other three LR ...


9
Alan L Goodrum, Roger E Tipley: Adjusting power budgets of multiple servers. Hewlett Packard Development Company, April 20, 2010: US07702931 (36 worldwide citation)

A method of adjusting power budgets of multiple servers within a data center comprises various actions. Such actions include, for example, organizing the multiple servers into hierarchical groups, dividing a total power budget among the hierarchical groups, and assigning power consumption levels to ...


10
Mark Taylor, Paul R Culley, Maria L Melo, Roger E Tipley: Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, September 3, 1996: US05553310 (33 worldwide citation)

Three prioritization schemes for determining which of several CPUs receives priority to become bus master of a host bus in a multiprocessor system, and an arbitration scheme for transferring control from one bus master to another. Each prioritization scheme prioritizes n elements, where a total of ( ...