Gigy Baror, Brian W Case, Rod G Fleck, Philip M Freidin, Smeeta Gupta, William M Johnson, Cheng Gang Kong, Ole H Moller, Timothy A Olson, David I Sorensen: Streamlined instruction processor. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, May 15, 1990: US04926323 (137 worldwide citation)

A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions fr ...

Rod G Fleck, Daniel Martin: Data processing unit with digital signal processing capabilities. Siemens Aktiengesellschaft, July 10, 2001: US06260137 (124 worldwide citation)

The present invention relates to a data processing unit comprising a register file, a register load and store buffer connected to the register file, a single memory, and a bus having at least first and second word lines to form a double word wide bus coupling the register load and store buffer with ...

Anthony F Istvan, Rod G Fleck, Robin Budd, Korina J B Stark, Marcellino Tanumihardja: Network-accessible control of one or more media devices. Vulcan, Perkins Coie, September 7, 2010: US07792920 (104 worldwide citation)

A content management (CM) system is provided to centrally control operation of one or more connected devices by issuing control requests and/or data requests. In some situations the connected device(s) include devices that control presentation of television programming-related content, such as digit ...

Brian W Case, Rod G Fleck, Cheng Gang Kong, Ole Moller: System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses. Advanced Micro Devices, Kenneth B Salomon, J Vincent Tortolano, October 11, 1988: US04777587 (91 worldwide citation)

An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condi ...

Rod G Fleck, Venkat Mattela, Eric Chesters, Muhammad Afsar: Data processing device with loop pipeline. Siemens Aktiengesellschaft, July 4, 2000: US06085315 (78 worldwide citation)

The data processing device according to the invention comprises an instruction providing unit having an input and an output, a pipeline unit for processing data having input and output stages, a loop pipeline unit for processing a loop instruction having input and output stages, said input stages of ...

Andreas Wenzel, Eric Chesters, Rod G Fleck, Gary Sheedy: On-chip debug system. Infineon Technologies, Fish & Richardson P C, February 4, 2003: US06516428 (60 worldwide citation)

An on-chip debug system includes a data band selector operable to transmit to an emulator the selected data bands generated by the selected components in an integrated circuit. The data band selector is directed by the emulator based upon instructions received from a host computer.

William M Johnson, Rod G Fleck, Cheng Gang Kong, Ole Moller: Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor. Advanced Micro Devices, Patrick T King, Kenneth B Salomon, J Vincent Tortolano, March 29, 1988: US04734852 (53 worldwide citation)

A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, ...

Rod G Fleck, Ole H Moller, Gigy Baror: Execution of a loop instructing in a loop pipeline after detection of a first occurrence of the loop instruction in an integer pipeline. Siemens Aktiengesellschaft, June 13, 2000: US06076159 (39 worldwide citation)

A data processor is disclosed which comprises a first pipeline for decoding and executing data instructions, a second pipeline for decoding and executing address instructions, a unit for issuing multiple instructions to the pipelines, a first set of registers being coupled with the first pipeline, a ...

Rod G Fleck, Roger D Arnold, Bruce Holmer, Vojin G Oklobdzija, Eric Chesters: Data processing unit with hardware assisted context switching capability. Siemens Aktiengesellschaft, October 3, 2000: US06128641 (37 worldwide citation)

The present invention relates to a method of context switching from a first task to a second task in a data processing unit having a register file with a plurality of general purpose registers and a context switch register, a memory comprising a previous context save area and an unused context save ...

Rod G Fleck, Klaus Oberlaender, Gigy Baror, Alfred Eder, Le Trong Nguyen: Data processing device with memory coupling unit. Infineon Technologies North America, Fish & Richardson P C, June 11, 2002: US06405273 (37 worldwide citation)

A data processing unit is disclosed with a register file having a plurality of registers. A memory having a plurality of n-bit input/output ports, and a coupling unit for coupling the memory with the register file, a memory address and select unit for addressing the memory banks are provided. The co ...