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Robin W Edenfield, William B Ledbetter Jr, Russell A Reininger: System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address. Motorola, Charlotte B Whitaker, October 13, 1992: US05155824 (103 worldwide citation)

A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a ...


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Christopher D Bryant, Robin W Edenfield: Low-latency circuit for synchronizing data transfers between clock domains derived from a common clock. National Semiconductor Corporation, Davis Munck P C, March 18, 2003: US06535946 (66 worldwide citation)

There is disclosed, for use in an x86-compatible processor, an interface circuit for synchronizing the transfer of signals between different clock domains derived from a common core clock, where the phase and frequency relationships between the different domain clocks are known. The interface circui ...


3
Robin W Edenfield, Ralph McGarity, Russell Reininger, William B Ledbetter Jr, Van B Shahan: Data processing system utilizes block move instruction for burst transferring blocks of data entries where width of data blocks varies. Motorola, Charlotte B Whitaker, February 9, 1993: US05185694 (41 worldwide citation)

A block MOVE instruction allows a programmer to issue an instruction to a loosely coupled system bus controller, thereby facilitating the execution of a memory to memory move of multiple data entries, utilizing a burst mode transfer onto the system bus for both reads and writes. The instruction allo ...


4
Robin W Edenfield, William B Ledbetter Jr: Data processor for reloading deferred pushes in a copy-back data cache. Motorola, Charlotte B Whitaker, March 23, 1993: US05197144 (40 worldwide citation)

A data processor is provided for reloading deferred pushes in copy-back cache. When a cache "miss" occurs, a cache controller selects a cache line for replacement, and request a burst line read to transfer the required cache line from an external memory. When the date entries in the cache line selec ...


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Russell A Reininger, William B Ledbetter Jr, Robin W Edenfield, Van B Shahan, Ralph C McGarity, Eric E Quintana: Memory access serialization as an MMU page attribute. Motorola, Charlotte B Johnson Whitaker, December 24, 1991: US05075846 (37 worldwide citation)

A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independentl ...


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Robin W Edenfield, Christopher D Bryant: System and method for synchronizing data transfer from one domain to another by selecting output data from either a first or second storage device. Advanced Micro Devices, September 28, 2004: US06799280 (30 worldwide citation)

An interface circuit is disclosed for synchronizing the transfer of data from a first clock domain driven by a first clock signal to a second clock domain driven by a second clock signal, where the phase and frequency relationships of the first and second clock signals are known. The interface circu ...


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