1
Robert W Horst: Active muscle assistance device and method. Tibion Corporation, Leah Sherry, Dechert, November 22, 2005: US06966882 (114 worldwide citation)

A method for controlling movement using an active powered device including an actuator, joint position sensor, muscle stress sensor, and control system. The device provides primarily muscle support although it is capable of additionally providing joint support (hence the name “active muscle assistan ...


2
Richard W Cutts Jr, Peter C Norwood, Kenneth C DeBacker, Nikhil A Mehta, Douglas E Jewett, John D Allison, Robert W Horst: Fault-tolerant computer with three independently clocked processors asynchronously executing identical code that are synchronized upon each voted access to two memory modules. Tandem Computers Incorporated, Graham & James, March 9, 1993: US05193175 (112 worldwide citation)

A computer system in a fault-tolerant configuration employs three identical CPUs executing the same instruction stream, with two identical, self-checking memory modules storing duplicates of the same data. Memory references by the three CPUs are made by three separate busses connected to three separ ...


3
Robert W Horst: Multiple-processor computer system with asynchronous execution of identical code streams. Tandem Computers Incorporated, Graham & James, May 31, 1994: US05317726 (110 worldwide citation)

A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via ...


4

5
Alan Heirich, Laurent Moll, Mark Shand, Albert Tam, Robert W Horst: Parallel pipelined merge engines. Hewlett Packard Development Company, June 22, 2004: US06753878 (99 worldwide citation)

An image generator is organized into a plurality of rendering engines, each of which renders an image of a part scene and provides the part image to a merge engine associated with that rendering engine. The image is a part image in that it usually contains less than all of the objects in the image t ...


6
Robert W Horst, William J Watson, David A Brown, David J Garcia, William P Bunton, David T Heron, William F Bruckert: System and method for configuring adaptive sets of links between routers in a system area network (SAN). Hewlett Packard Development Company, September 27, 2005: US06950428 (89 worldwide citation)

Adaptive sets of lanes are configured between routers in a system area network. Source nodes determine whether packets may be adaptively routed between the lanes by encoding adaptive control bits in the packet header. The adaptive control bits also facilitate the flushing of all lanes of the adaptiv ...


7
Robert W Horst: Memory system using linear array wafer scale integration architecture. Tandem Computers Incorporated, Townsend and Townsend Khourie and Crew, February 15, 1994: US05287472 (88 worldwide citation)

A cell architecture for use in a linear array wafer scale integration includes a plurality of multiplexers, each associated with a boundary of the cell, and each selectively operable to permit ingress to and egress from function logic of the cell by neighboring cells. Each multiplexer is configured ...


8
Robert W Horst: Logical, fail-functional, dual central processor units formed from three processor units. Tandem Computers Incorporated, Townsend and Townsend and Crew, November 17, 1998: US05838894 (87 worldwide citation)

A computing system includes a pair of central processor units structured to operate in substantial synchronism to each execute the same instruction at substantially the same moment in time of identical instruction streams to achieve a logical central processor unit with fail-functional operation. On ...


9
Robert W Horst, David J Garcia, William Patterson Bunton, William F Bruckert, Daniel L Fowler, Curtis Willard Jones Jr, David Paul Sonnier, William Joel Watson, Frank A Williams: Self-checked, lock step processor pairs. Compaq Computer Corporation, Oppenheimer Wolff & Donnelly, May 15, 2001: US06233702 (85 worldwide citation)

A multiprocessor system includes a number of sub-processor systems, each substantially identically constructed, and each comprising a central processing unit (CPU), and at least one I/O device, interconnected by routing apparatus that also interconnects the sub-processor systems. A CPU of any one of ...


10
John C Krause, David J Garcia, Robert W Horst, Geoffrey I Iswandhi, David Paul Sonnier, William Joel Watson, Linda Ellen Zalzala: Network message routing using routing table information and supplemental enable information for deadlock prevention. Tandem Computers, Townsend and Townsend and Crew, June 22, 1999: US05914953 (74 worldwide citation)

A processing system includes multiple processor units and multiple input/output elements communicatively interconnected by a system area network having a plurality of multi-ported router elements. Communication between the system elements uses message packets that contain, among other things, destin ...